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Enhancing test quality in advanced CMOS nodes

Posted: 23 Jan 2015     Print Version  Bookmark and Share

Keywords:CMOS  IC design  Design for Testability  DFT  SoC 

Avoid bad patterns: Excessive switching in capture mode during transition testing also results in higher power dissipation. The dissipation might be much higher than mission mode switching too. Excessive capture switching results into higher IR drop which leads to a higher chance of failure with lower voltage. This scenario can be seen with following shmoo plots. Left shmoo plot is meant for patterns without power budget having high switching and right shmoo plot is for the same vector generated with power budget ensuring low capture switching. Most of the ATPG EDA tools come with power-aware features too. It is strongly recommended to use the proper power budget as per design requirements to generate patterns.

Use of sanity check and simulation after pattern generation: The feature of Sanity check is generally provided in the conventional ATPG tool. This feature checks the correctness of the generated patterns. During our project execution, we have experienced such scenarios where the generated patterns fail sanity checks due to some applied constraints. The vector simulation needs to be done to check pattern correctness against the actual design. The vector simulation with timing can help verify the design against timing constraints.

Use of Advanced Fault model: At small-scale technology nodes, new defects arise which demand the use of advanced fault models like Smaller delay, Hold Time, Path delay and Iddq. Test quality can be improved by applying multiple tests that target different classes of faults. There are test models other than conventional Single Stuck-at and Transition fault models which can help improve the overall defect coverage and test quality.

Conclusion
Test quality is a major responsibility of DFT personnel. Various test strategies for improving test quality have been discussed in this article. Test escapes in the IC design can cause failures in system testing. Test escapes can be avoided by achieving high defect coverage, as essential to attaining high yield. While working on small-scale CMOS technology nodes, we have faced similar issues. Based on that experience, we have discussed our views on achieving better defect coverage, and in turn high yield.

About the authors
Parth Rao, Chintan Panchal, Harsh Parikh and Ankit Shah are engineers at eInfochips.


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