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How to prevent errors and delays in SoC design

Posted: 10 Oct 2014     Print Version  Bookmark and Share

Keywords:SoC  verification  clock domain crossing  28nm 

Editor's Note: In this article, Graham Bell of Real Intent saw similarities between system-on-chip (SoC) and verification engineers and cowboys of the Wild West as both struggle to control and move a big "herd."

In the stories of the Wild West from the 1800s, the image of a cattle drive often is depicted. A small team of cowboys deliver thousands of heads of cattle to market. The cowboys spend many days crossing open land until they reach their destination—one with stockyards to accept their precious herd, and a rail station to deliver it quickly to market. Along the way, there are dangers, including losses by predators and mad stampedes by cattle rushing blindly when frightened or disturbed. The primary job of the cowboys is to keep the herd on track and settled as they move to ship-out.

I see immediate parallels between the cowboys of the Wild West and today's SoC design and verification engineers. Cowhands struggle to control and move a big herd. Similarly, today's design teams grapple with how to keep a project on target and converging to tape-out, and successful when the gate count of SoCs has become so large it can stretch and even overwhelm their ability to stay on track. How big are these new SoCs?

The Xbox One gaming console, for example, uses 5 billion transistors, which is equivalent to 1.25 billion digital gates. Its AMD-designed SoC produced at TSMC on a 28nm process combines eight Jaguar CPU cores and Graphics Core Next (GCN)-class integrated graphics. (See Figure 1.)

 XBOX ONE

Figure 1: XBOX ONE is an example of a modern SoC with more than 1 billion digital gates. (Source: Microsoft Inc.)

Another example, pictured on below, is Nvidia's GK110 GPU (also made on TSMC's 28nm process), which has 7.1 billion transistors. This translates to nearly 2 billion digital gates. These are not just big chips but giant chips.

 Nvidia's GK110 GPU

With each smaller semiconductor node foundries provide, more gates can be squeezed into the same die size. In parallel, many different kinds of design blocks and intellectual property (IP) are employed, usually created by third parties, to accelerate the implementation of the design objectives. The interaction of the various blocks across various power and timing conditions adds a new kind of complexity to the design. The result is a "herd" of interfaces with thousands of different crossings that must be checked and verified to ensure the design does not run off into a fatal operating condition.

It would be great to have the luxury of several hundred design and verification engineers to verify all possible failures in these giant SoCs, but that is not usually the case. Typically, a small team relies on design automation software to manage the complexity of the verification challenge.


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