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ARM redesigns microarchitecture for embedded controllers

Posted: 08 Oct 2014     Print Version  Bookmark and Share

Keywords:ARM  Internet of Things  embedded controller  Cortex-M7  microarchitecture 

ARM has recently unleashed what it says is a completely revamped microarchitecture for an embedded controller. According to the company, Cortex-M7 is not an extension of its previous line-up that includes the M3 to the M4. Instead, the device is targeted at the increasingly challenging user interfaces and performance requirements by the connected world, enabled by the Internet of Things.

"It's a clean sheet and so it doesn't look like anything we have built before," said Richard York, VP of embedded CPU marketing at ARM. "There is an insatiable access in the connected world and more interactivity, and customers and industry are demanding better user interfaces. That means the performance needs in embedded micros are going up and up. We looked at what the Cortex-M4 was doing and the feedback was to double the performance."

Cortex-M7 pipeline

Cortex-M7 pipeline. (Image: ARM)

The execution pipeline has been made longer, reaching six stages, and it's dual issue, with a separate MAC pipeline and an optional double precision execution unit. But the latency has been tightened up so that it stays at 12 cycles, like the M4. "It's a longer pipeline but there's careful engineering to make sure we don't make interrupt performance worse." The microarchitecture also adds an instruction and data cache, which is unusual for a microcontroller, but the higher performance allows the microarchitecture to meet the latency requirements within the frequency limits of the on-chip flash memory. "What we did was look at the other processors to re-engineer them, but we need to match the short pipeline to the flash memory as we don't go mad on frequency."

As ever, it's the infrastructure around the execution unit and the core that actually makes the main difference for the overall performance. Around the 32bit execution unit, the AXI bus has been expanded to 64 bits wide so that two independent loads can be executed at the same time. All of this allows developers to run Java or Matlab directly.

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