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ARM takes 64bit approach to datacentres

Posted: 02 Sep 2014     Print Version  Bookmark and Share

Keywords:ARMv8  64bit  server  datacentre 

The "Seattle" chip is AMD's first 64bit ARM-based processor and combines eight ARM Cortex-A57 cores running at 2GHz and above. Seattle is a dense server processor for datacenter applications where the key driver is performance/dollar/watt, says AMD. One way to tackle this is to increase the instructions per clock (IPC) and reduce the high cache miss-rates so Seattle, with smaller cores and caches, can deliver the equivalent performance as traditional server processors with large cores and caches, but using much less power and area.

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The memory structure of Seattle combines L1, L2, and L3 cache.

Cache optimisation has been a focus for processor designers for decades, and there is no real surprise in the design of Seattle. Each of the A57 cores has a 48kB 3-way set associative, parity protected instruction cache to feed the processing engine, with a 32kB 2-way associative data cache. Each core then shares a 2MB 16-way L2 cache with a neighbour.

The bonus from the latest 28nm process technology is it then being able to put a massive 8MB L3 16-way cache in the centre of the chip with a snoop filter to ensure the L2 caches are coherent and minimise the hit from a cache miss or refresh. The wider memory sub-system then also becomes important, with two 64bit DDR3/4 channels with ECC and each device supporting up to 128GB of DRAM to get the flow of data as stable as possible through the device and making the most of all those cycles.

AMD has taped out samples, and there is a demonstration board running an ARM-optimised version of Linux based on RHEL, Apache 2.4.6, MySQL 5.5.35, and PHP 5.4.16. The server was then used to host a WordPress blog that included streamable video. General availability is expected in the fourth quarter.

- Nick Flaherty
  EE Times Europe


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