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Power/Alternative Energy  

Simple, cost effective EV charger design

Posted: 30 Jul 2014     Print Version  Bookmark and Share

Keywords:electric vehicles  hybrid vehicles  pay-to-charge  microcontrollers  charging station 

The metering system can be easily partitioned to include all of the functions into a single embedded processor using a dual-core processor with a sub-system. Many silicon vendors also offer multiple solutions for radio communications and system-level isolation. The system can be broken into smaller sub-segments based on the functions listed above, starting with the requirement for metering and determining the kilowatt hours (kWh) to be billed to the customer.

The metering stage takes advantage of the analogue system of the dual-core device, utilising the internal ADCs and processing power of the CPU (in this case, the C28x DSP core) combined with a current transformer. For increased tamper resistance, a shunt resistor circuit may also be added. When combined with a real-time clock, the processing for measuring kWh becomes a standard voltage and current measurement that can easily be handled with a combination of up to seven analogue to digital converter inputs of the C2000 MCU, depending if both the current transformer and shunt resistor are used in parallel as well as the total number of phases.

By utilising a digitally controlled closed loop over-current protection scheme system-level safety is increased with the addition of a physical relay on the main charging bus. With the on-chip analogue comparators of the dual-core device, their outputs tied to a standard GPIO, and using the relay driver (DRV110), a closed loop "smart" circuit protection scheme can be implemented that offers both user or CPU-controlled reset while maintaining low-power architecture and reducing the number of required external components.

There are also several elements deployed in dual-core microcontroller architectures that can be utilised to enhance the overall safety of the system. With two independent processors in the controller, one can be used to check for proper operation of the other one on a scheduled basis. In addition, critical computations can be run on both processors in parallel and checked for correctness before the result is used by the system.

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