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Taking a closer look at phase change memory

Posted: 27 May 2014     Print Version  Bookmark and Share

Keywords:Macronix International  phase change memory  PCM  ReRAM  RRAM 

What if the device is in the high resistance (0 data) foreground state? In that case, a similar write "1" pulse sequence will be applied. Each pulse will be of increasing voltage amplitude but only sourced with sufficient current to set the device. If the write 1 pulse sequence is applied to a device already in the logic 1, then a pre-read would be one solution that would avoid over-writing problems.

For writing background data, the problem is a little more difficult and will most likely need to involve a two-step process. The second image suggests means of writing background data. Initially pre-read, if the foreground is in the 1 state; then apply the reset sequence, which will carry the background data to the 0 foreground (blue line) state; then apply a single set pulse (orange line) to achieve the desired set background state. The upper curves of image 2(a) and 2(b) are for transitions 1(00) to 1(11) and 1(11) to 1(00) respectively.

PCM data rate

For transition within the 0 state, apply the pulse sequence this time with a current source that will write the desired set state. Then apply the reset pulse sequence. Figure 2(c) and (d) illustrate the background data transitions of 0(00) to 0(11) and 0(11) to 0(00) respectively.

That speculation does not represent anything new and could be achieved with some clever circuit design with existing PCM devices, assuming that sufficient number of discrete levels can be obtained. For the 4bit cell that will be reported in the IBM paper, and using the speculative approach illustrated here, some 16 discrete resistance levels would be required.

The authors of IBM's double density memory paper must have found some other way to get to the same end point. Clearly, the role of stressing must be more than just thermal. It will be interesting to see how the double-density approach deals with the problem of drift and many of the other outstanding PCM problems. It looks as though this paper may be the PCM highlight of VLSI 2014.

The second PCM paper (11.2) from the IBM-Macronix project is titled "Towards the Integration of both ROM and RAM Functions Phase Change Memory Cells on a Single Die for System-on-Chip (SoC) Applications." This paper will address the problem of integrating different memory functions on the same chip.

The team claims to have discovered a means of changing the characteristics of a PCM memory from RAM-like to ROM-like, that is fast write/erase or long data retention. If the title of the paper can be taken literally, meaning one-time programmable ROM rather that a long retention time re-writeable PCM, then one is tempted to ask: What's new? It has always been possible to change a PCM into a ROM by operating it as a PROM or even an anti-fuse by over-driving the cell.

The dual-role memory effect is not, as might be expected, to be obtained by some complex changes in active material composition or changing the write/erase conditions; it uses the same active material. The change is of the form of the dielectric cap that covers the PCM cell. The pre-Symposium preliminary information indicates that by using a low temperature silicon nitride capping material, the RAM-like memory characteristics are obtained, with claimed write times of 20 ns. With the silicon nitride capping material formed at high temperature, the data retention time is greater than 400 years at 85°C.

Continuing in our speculative vein, without detailed knowledge of the memory cell structure, this raises a number of possibilities as to the source of the effect. IBM already has some patent coverage in the area of memory structures that apply strain to phase-change material. It would be expected that that silicon nitride films formed at different temperatures would be under different levels of strain as well as having different densities, different thermal conductivities, and coefficients of thermal expansion.

There is also a possibility that these new devices rely on some of the earlier work from the IBM/Macronix team. In that work, complex electrode structures and thermal barrier layers were used to reduce reset current densities, reduce thermal losses, and improve the efficiency of the write set/reset operation.

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