Global Sources
EE Times-India
Stay in touch with EE Times India
 
EE Times-India > FPGAs/PLDs
 
 
FPGAs/PLDs  

Lattice intros companion FPGA boasting up to 85K LUTs

Posted: 15 Apr 2014     Print Version  Bookmark and Share

Keywords:Lattice Semiconductor  FPGA  LUT  microserver  small cell 

Lattice Semiconductor has announced the ECP5 FPGA family aimed at the fast growing and high-volume markets such as small-cells, microservers, broadband access or industrial video. As a companion chip delivering design flexibility to ASICs and ASSPs, the IC comes in various options offering from 25-85K look-up tables (LUTs) at a cost 40 per cent lower than alternatives while providing twice the functional density of competing solutions, noted the company.

"Most of our competitors focus on making larger devices with complex routing, then try to scale the FPGAs back to offer smaller devices, but their architecture does not scale back very well," said Bruce Fienberg, director of corporate communications at Lattice Semiconductors.

"Because we focus on devices below 100K LUTs, we are able to simplify routing for a more efficient use of silicon, hence the higher density of our 40nm designs versus our competitors' devices built in 28nm," he added.

ECP5 FPGA

The devices are specifically designed to closely match a number of applications, with improvements on the DSP block and support for very low cost and low power SERDES links. The ECP5 FPGAs provide the flexible connectivity required in outdoor small-cells, at extremely low-cost. They can also enable a smart small form-factor pluggable (SFP) transceiver solution for broadband access equipment, including integrated operation and maintenance, stated Lattice.

Outside of communications, ECP5 devices offer low cost, low power PCI Express side-band connectivity for microservers. For industrial video cameras, ECP5 FPGAs can implement the entire image processing functionality in a device that consumes under 2W. Enhancements leading to 30 per cent lower total power than other FPGA solutions include stand-by mode operation of the individual blocks including SERDES, dynamic IO bank controllers and reduced operating voltage.

This enables single channel 3.25Gb/s SERDES functions starting below 0.25W, and quad channel SERDES functions starting below 0.5W for supporting a broad range of interface standards, including DDR3, LPDDR3, XGMII and 7:1 LVDS, PCI Express, Ethernet (XAUI, GbE, SGMII) and CPRI.

The ECP5 FPGA family is available and supported in version 3.0 of the Lattice Diamond software tool.

- Julien Happich
  EE Times Europe





Comment on "Lattice intros companion FPGA boasti..."
Comments:  
*  You can enter [0] more charecters.
*Verify code:
 
 
Webinars

Seminars

Visit Asia Webinars to learn about the latest in technology and get practical design tips.

 

Go to top             Connect on Facebook      Follow us on Twitter      Follow us on Orkut

 
Back to Top