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Hardware, software implications of endianness

Posted: 14 Apr 2014     Print Version  Bookmark and Share

Keywords:software programmers  endianness  computing processor  compilers  CPU 

When the hardware IP block extracts the two 32bit data units on a little endian bus, it will need to extract the first data unit (0x44332211) from the lower four byte lanes (0-3) and the second data unit (0x88776655) from the higher four byte lanes (4-7). On a big endian bus, it is the other way around. Note that, because the software stored input data in memory in 32bit data units, we did not have to worry about the byte order within each 32bit data unit. Between the two endianness modes, the byte order within a 32bit data unit is reversed when storing in memory and is reversed again when placing on the bus.

Thus, when a hardware block obtains input data or gives out output data on a bus, there are several considerations that hardware IP block designers need to be aware of:
 • What is the unit size of data being processed in the hardware IP block?
 • In case of input data, is the source of data another hardware IP block or memory? In what order and what unit sizes is the input data prepared? Similar considerations apply in case of output data
 • What is the bus transfer transaction size?
 • What is the endianness of the bus?

Let us switch gears and think for a moment that a hardware IP block was designed for a specific endianness, irrespective of the endianness of the system. Examples of this situation are discrete hardware devices connected on a PCI bus. A PCI bus is defined in specification to be little endian and devices connected to it therefore expect data to appear little endian on the bus. The host processor to which the PCI device is connected may be big endian or little endian. In this case, it is the responsibility of some software component (device driver) or some hardware component (an intermediate bridge between the host and the PCI device) to take into account the endianness of the host processor and use a specific byte sequence on the bus (reversing the sequence of bytes if required) while writing or reading the data from the PCI device.

This situation is similar to a SoC whose endianness (that of CPU core and bus infrastructure) is configurable to be either little endian or big endian at boot time, but contains a hardware IP block with a fixed endianness. Let us say the hardware IP block is designed with the assumption that the bus is little endian. In case the SoC is configured as little endian, the sequence of bytes in CPU's memory will be preserved when transferred to the IP block's memory. In the event that the SoC is configured as big endian, for each transaction the sequence of bytes in the IP block's memory will be reversed relative to the byte sequence in the CPU's memory. To circumvent the reversal, the sequence of bytes needs to be reversed for each transaction over the bus. This may be done by software when preparing the data in the CPU's memory or by an intermediate hardware bridge between memory and the IP block. In the following example, we illustrate how software can organise the data in CPU's memory before the (little endian) IP block reads it. We assume the hardware IP block processes input data in 8bit units and obtains the input data in 64bit transactions.

The byte sequence would now be the same for each transaction on the bus regardless of the endianness of the bus:

The same sequence of byte data units on the physical byte lanes of the bus serves the hardware IP block well to read out the bytes in the same fashion regardless of the SoC's boot time endianness configuration.

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