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PLLs in IC-based clock distribution system (Part 2)

Posted: 21 Feb 2014     Print Version  Bookmark and Share

Keywords:Timing  oscillator  phase-locked loop  PLL  clock distribution 

In Part 1 of this series, we discussed phase-locked loop applications and advantages in clock distribution systems compared to conventional oscillators. In this article and the next we will discuss significant parameters of PLL-based clock distribution systems that need to be considered during design (such as the importance of accurate timing of the clock when exercised).

Wide deviations in clock positions may cause a system to malfunction. These deviations in time domain are referred as "jitter". Jitter can be classified into categories such as period jitter, cycle-cycle jitter, RMS jitter, long-term jitter, and phase jitter. Here we will keep the focus on phase jitter, which when examined in the frequency domain is also referred to as "phase noise".

Defining phase noise and phase jitter
Phase noise and phase jitter are the key parameters for any clock distribution system, as the quality of the clock signal is heavily dependent upon its phase noise and jitter. The maximum speed of digital I/O is limited by timing errors in clocks. With continuing advances in technology and increased timing precision requirements, it is essential to have clocks with accurate edges and high stability.

Ideally, there should no variation in clock edges from their expected position. In practice, clock sources are highly affected by noise, which in turn causes variation in clock edges from their ideal position. This is called "jitter". PLL-based frequency synthesisers are mainly designed to ensure the accuracy of the output frequency under specified operating conditions. One of its critical requirements includes phase noise and phase jitter performance, where phase noise represents clock signal noise in the frequency domain and jitter is the time domain representation of clock signal instability. "Time" and "phase" can be used interchangeably to quantify jitter and phase noise.

Excessive jitter in a system causes higher bit error rates that may exceed system-level requirements. RF and A/D data conversion applications require very low phase noise clocks. In RF applications, increased phase noise can create channel-to-channel interference, degrading RF signal quality. In ADC applications, higher phase noise can limit the signal-to-noise ratio (SNR) and increase quantisation error.

One of the major issues being faced by PLL designers is the phase noise phenomenon. Phase noise is an undesirable entity that is present in all real-world oscillators and signal generators that can cause distortion or complete loss of incoming information in traditional receivers. It is therefore necessary to understand and to quantify phase noise so that its effects on the higher level product are minimised.

Understanding phase noise
To understand what phase noise is, let's start by looking at an ideal sinusoid signal. A sinusoidal wave is the fundamental form of a periodic analogue signal. A sinusoid signal can be expressed as:

where A = Peak amplitude of signal, f = Frequency and Φ = initial phase (i.e., the absolute position of the waveform relative to an arbitrary origin). Phase is measured in degrees (°) or radians. A time domain plot of any real-world signal specifies the signal amplitude at any instant of time, and it does not express explicitly information of the signal's phase or frequency.

On the other hand, by taking the Fourier transform of a signal, we can obtain signal information in the frequency domain, which represents the signal's peak amplitude with respect to the frequency components that comprise it. The time domain and frequency domain are just two ways of representing a signal to capture different information. When talking about time variation in a signal, one can be considered to be talking about phase or frequency variation, which can be correlated as:


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