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Cadence RTL Compiler incudes physically aware synthesis

Posted: 22 Nov 2013     Print Version  Bookmark and Share

Keywords:Cadence Design Systems  RTL Compiler  SoC  chip design 

Cadence Design Systems Inc. has announced the Encounter RTL Compiler version 13.1 that includes a suite of physically aware RTL synthesis capabilities. The company said the latest features deliver up to 15 per cent improvement in power, performance and area on today's most complex advanced node chip designs that face timing or congestion challenges. The capabilities are part of a production-ready physical synthesis engine that lets engineers use physical aware techniques at the earliest phases of synthesis for better silicon results.

As geometries shrink beyond 28nm, changes in interconnect characteristics make it much more difficult to achieve optimal timing and closure. The RTL Compiler capabilities let design teams address these challenges earlier in the design process so they can achieve faster timing closure, while improving performance, power and area.

The RTL synthesis capabilities include physically aware structuring, mapping, multi-bit cell inferencing and design for test that offer significant benefits for Cadence customers. Physically aware structuring and mapping can improve performance by more than 10 per cent and area by more than 15 per cent on complex SoCs by considering pin and register placement when deciding which micro-architectures to synthesise to, and how to balance them. Physically aware multi-bit cell inferencing can lower power by more than 10 per cent by merging single registers into multi-bit registers that share a clock.





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