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Renesas touts high-performance 32bit RX CPU core

Posted: 15 Nov 2013     Print Version  Bookmark and Share

Keywords:Renesas Electronics  CPU core  embedded device  MCU  FPU 

Renesas Electronics Corp. has developed what it describes as a high-performance 32bit RX CPU core for embedded devices in the consumer, industrial and office equipment fields. The RXv2 core features increased performance from 3.2 to 4.0 CoremarkMHz or 2.0DMIPS/MHz, with a maximum frequency of 300MHz in 40nm. It will also feature enhanced DSP and FPU capabilities. The core architecture will benefit applications that require a combination of higher performance, and DSP and FPU capabilities on a single MCU, such as those for factory automation, motor control, signal analysis, audio filtering, image processing and connectivity, detailed the company.

The RXv2 core is backward compatible with the Renesas RXv1 CPU core employed in the existing RX family of 32bit Complex Instruction Set Computer (CISC) MCUs. The RXv2 contains all the instruction sets available in the RXv1 core, therefore applications developed for the RXv1 will be binary compatible with the latest core.

The RXv1 core combined the increased processing capacity made possible by the ability of CISC MCUs to execute complex instructions with Reduced Instruction Set Computer (RISC) streamlining techniques developed for the CPUs of other Renesas MCUs. Specifically, CISC features such as variable-byte instructions are combined with RISC features such as general register machine, Harvard architecture and five-stage pipeline. The RXv2 core leverages this architecture to deliver improved computing performance, power efficiency and high code efficiency via a dual-issue pipeline structure and Advanced Fetch Unit.

There has been a growing demand for improved processing performance in single-chip MCUs for use in embedded devices in order to provide higher added value and accommodate increased system complexity. In particular, for motor control and mechanism control applications in the industrial and office equipment fields, there is a need for better CPU processing performance in order to achieve improved real-time performance and enhanced stability. At the same time, reducing power consumption remains an important issue. Increasing the operating frequency is a common method of boosting performance, but simply raising the frequency also increases the operating current flow and has a variety of adverse effects, such as requiring redesign of the power supply circuit or countermeasures to deal with noise on the system board. This in turn increases the overall system cost and lengthens the time needed for development. Renesas has developed the RXv2 core to meet these demands, retaining backward compatibility with the RXv1 core, while delivering improved CPU performance and reduced power consumption.

One feature common to all RX family CPUs, including the RXv2 core, is the floating point unit (FPU), which is essential for tasks that require numerical analysis in real time such as multimedia processing and motor control. While most CPUs incorporate a coprocessor-type FPU, the RX family of CPUs uses an instruction set that employs general registers for FPU operations. The FPU also features an improved pipeline processing structure and improved execution time. The number of processing cycles has been further reduced in the RXv2 by adding a DSP instruction and reducing processing cycles of the single-precision floating point, resulting in even better computing performance. The RXv2 features two dedicated 72bit accumulators (the RXv1 has a single 64bit accumulator) and a 1-cycle MAC instruction, enhancing the DSP function and enabling the DSP to handle even 32bit fixed point multiply-and-accumulate operations flexibly. In addition, the RXv2 can perform DSP/FPU operations and memory accesses simultaneously, substantially boosting the signal processing capability.

When used in combination with the C compiler from IAR Systems, the RXv2 core delivers performance in excess of 4.0 Coremark/MHz. This is equivalent to a performance increase of 25 per cent (target value) over the existing RXv1 core when operating at the same frequency.


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