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SK Hynix licences 3D IC from BeSang

Posted: 30 Oct 2013     Print Version  Bookmark and Share

Keywords:SK Hynix  3D chip  BeSang  TSVs 

South Korean memory chip maker SK Hynix Inc. has licenced the 3D chip technology of BeSang Inc. SK Hynix will licence what BeSang calls its "True 3D IC" process, which uses a low-temperature process to build multi-layer 3D integrated circuits one layer at a time using traditional vias, instead of stacking finished die using through-silicon-vias (TSVs).

The patent-licence agreement with SK Hynix calls for technology transfer including updates based on a service fee for a five-year period, but does not include collaboration. Also the agreement is non-exclusive, allowing BeSang the opportunity to strike similar deals with other chip manufacturers.

SK Hynix specialises in DRAM, NAND flash, solid-state drives (SSDs), and image sensors, but the deal extends beyond memories to system ICs and even foundry business in the future. BeSang claims to have demonstrated that its 3D IC process works, not only with DRAMs, but with a wide variety of integrated circuit types, including CPUs, DSPs, GPUs, ASICs, FPGAs, SoCs, NAND flash, SRAM, and image sensors.

BeSang was founded in 2008 by CEO Sang-Yun Lee, who has been perfecting its 3D IC process along with former Samsung engineer Junil Park, developer of the first atomic layer deposition tool for high-k dielectrics. BeSang's novel process requires no TSVs or special equipment to fabricate multi-layer 3D ICs.

"Multiple device layers can be sequentially stacked on the top of existing devices with conventional semiconductor equipment," said Junil Parks, senior vice president and head of research and development at Besang, in an exclusive interview with EE Times. "And unlike other 3D IC technologies, BeSang's True 3D IC can be realised with low-temperature processes, which does not affect the circuitry on lower layers."

BeSang's technology works by fabricating a standard CMOS logic wafer first, then overlaying it with a layer of protective dielectric. To fabricate multiple layers of memory atop the logic layer, a donor wafer with three layers of doped silicon (n-p-n) is bonded to the top of the assembly with no need for alignment. Next the n-p-n layer is etched with perfectly aligned vertical n-p-n channels for surround gate transistors (SGTs) that connect to the logic layer below with conventional vias. Metal or polysilicon is then deposited using a low-temperature process to add the surround gates.

Finally, capacitors are fabricated atop each transistor on the 3D IC, thus transforming them into DRAM cells stacked on top of their logic chips. By repeating with another protective dielectric layer and donor wafer, any number of DRAM layers can be added atop a single logic chip.

"With BeSang's process, semiconductors can achieve densities of 1 million interconnections per millimeter, compared to 10,000 interconnections per millimeter for stacked die using TSVs and just 100 interconnects per millimeter for stacked packages," says Parks.

When applied to DRAMs, BeSang's 3D IC technology aims to increase the areal density of DRAMs without having to scale-down feature sizes, a boon to memory makers who are facing physics limitations to future downsizing of features. SK Hynix's 3D DRAMs could begin appearing as soon as 2014.

R. Colin Johnson

EE Times





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