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Improving the decap placement methodology

Posted: 18 Oct 2013     Print Version  Bookmark and Share

Keywords:Power integrity  QoR  decoupling capacitances  decap  placement 

The total intentional cap in figure 5 is the actual decap of the physical decap cells in the design. There are a total of 10656 Decap cells that are 'traditionally' placed in one DVD analysis setup, and placed as per the proposed flow in another DVD setup. The total decap from these physical decap cells is 0.88nF in both the setups.

As we can see, the amount of intrinsic capacitance (as a decap source) from non-switching instances is very high as compared to intentional decap cells. It is hence, quite likely that the traditional decap strategy would place decap cells at places where the non-switching device-cap is already very high, making these decap cells redundant and ineffective while adding to leakage.

Figure 4: Design statistics.

Figure 5: Sources of decaps.

Figure 6: DVD drop map around the last level clock-tree buffer region with traditional decap strategy (left) and with proposed decap strategy (right).

On the other hand, the placement of decap cells at regions in the chip where the non-switching device-cap is expected to be low becomes very critical. The last-level clock tree buffer along with its proximity to several flops is one such region that would have higher toggling or simultaneous switching resulting in low non-switching device-cap and also higher switching peak current due to increased fanout load of this last-level clock tree buffer. Our proposed decap strategy places the decap cells in these regions ensuring these are truly effective.

A dynamic voltage drop analysis comparison around the last-level clock tree buffer region between traditionally placed decap cell setup and our proposed decap cell placement setup demonstrates the value of our proposed decap strategy.

The DVD analysis was done with Ansys-Apache RedHawk tool. Figure 6 shows the Dynamic Voltage Drop (DVD) map of a region with several last clock tree buffers. The placed decaps encircled in figure 6 (right) are abutted with these last clock buffers in our proposed decap strategy.

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