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Effective hardware/firmware co-design (Part 2)

Posted: 19 Sep 2013     Print Version  Bookmark and Share

Keywords:Buffer  embedded systems  interrupt  hardware  firmware 

DMA Features. A distinct advantage of hardware is the ability to do things in parallel. A DMA controller is transferring data in and out of memory. It can perform some basic tasks on that data without impacting the data throughput. One that has proved useful is a byte swapping ability. This can help in a few different ways:
 • The block can work with bigor little-endian processors.
 • It can facilitate data exchanges between blocks or processors of different endianess.
 • It can handle data downloaded to the device in either endianess.
 • Minimise the amount of time firmware has to spend on byte swapping, a very tediousfirmware task.
 • It could workaround endianess problems within the chip.

Tale from the Trenches. The incoming DMA of a block was incorrectly wired to the bus with the wrong byte order. Since that DMA had a byte-swapping feature, firmware was able to configure it to swap it back before the data went on into the block. This feature averted an expensive chip re-spin.

A common problem with embedded systems is memory stomps and corrupted data. Building a CRC and/or a checksum generator inside the DMA can provide a data signature that provides a sanity check on the data. Comparing the signature to data when written to memory by one block to the signature of the data when read by another block will catch memory data corruption while in memory.

Since data corruption problems are typically not noted until the end of the pipeline, looking at the DMA controller CRC and/or checksum signatures at the various steps within the pipeline may give clues to corruption problems. Note that the signature may not be the same throughout the data pipeline.

A block processing the data is likely to be modifying the data. So the DMA controller signature when the block reads the data may be different than the signature when it writes the data.

Adding the CRC and/or checksum generator in the DMA controller module that is instantiated throughout the chip will ensure that the same algorithm is used in all locations.

Best Practice Tips. Include a byte-swapping capability in the DMA controller module instantiated throughout the chip. Include a CRC and/or a checksum generator in the DMA controller module instantiated throughout the chip.

Sharing I/O Pins. Given that pins on a package are expensive, it is not uncommon for more than one block to share pins. Output signals from more than one block to the same output pin must be muxed since only one block can be allowed to drive the pin.

Input pins that fan to more than one block should also be switched such that only one block will get the actual signals. This will prevent inadvertent interrupts and responses from blocks that are supposedly not active.

The input signals not currently configured to be connected to the pin still needs to be configured to an appropriate asserted or deasserted level, such as deasserted to indicate that the block is not ready for transmission.

Figure 1 illustrates this pin sharing between three blocks: A, B, and C. Block A is currently selected to be connected to the pins. The signal coming out of block A is routed through the mux to the output pin.

The output signals of blocks B and C are not connected and therefore ignored. The incoming signal is routed through the mux to block A. The input signal of block B is tied high while not connected to the pin and the input signal of block C is tied low.

Figure 1: Three blocks using the same I/O pins, but only one at a time.

Best Practice Tips: For each chip output pin connected to multiple blocks on the chip, multiplex the block output lines to select which block controls the signal on the chip output pin at any given time. For each input pin connected to multiple blocks on the chip, multiplex the input line to select which block (or blocks) receives the signal at any given time.

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