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Boost ASIP code generation, compilation (Part 1)

Posted: 05 Sep 2013     Print Version  Bookmark and Share

Keywords:Embedded processors  algorithms  Software developers  ASIPs  DSPs 

Embedded processors are usually selected for their ability to execute particular algorithms, whether they are standard parts such as DSPs or application-specific instruction processors (ASIPs) designed for a particular project. Back-end compiler phases are often keys to exploiting the relationship between the processor architecture and the application. General-purpose compilers are designed to compile code for a wide range of purposes.

Compilation speed is often important—when designing large software systems, programmers must be able to run through the write/compile/execute/debug cycle quickly. Software developers for embedded systems have somewhat different needs. Embedded software must often meet hard targets for execution time, energy consumption, or code size.

As a result, a number of compilation algorithms developed for embedded systems are optimisation algorithms; general- purpose compiler writers often have to balance the requirements of different users at the expense of precise constraint satisfaction. Embedded software developers may also be willing to wait longer for the compiler to run if it performs useful functions.

Figure 1: Major steps in code generation.

While some stages may require fast write/compile/execute/ debug cycles, other stages may require careful tuning to meet performance, size, or energy constraints. If the compiler can perform those tasks with minimal intercession by the programmer, then programmers generally are happy to wait for the compiler to do its work. As illustrated in figure 1, the major steps in code generation [1] are as follows:

1. Instruction selection determines which opcodes and modes are used to implement all the operations in the program. The abstract program must be covered by the selected instructions. They may also be selected to minimise program cost such as size or performance.

2. Register allocation determines which registers are used to hold the values in the program. In a general-register machine, in which all instructions can operate on all registers, register allocation can be performed strictly after instruction selection.

Many ASIPs and DSPs do not fit that model—some important instructions may work on only one or a few registers. In such cases, instruction selection must allocate critical values to registers, and the register-allocation phase allocates the remaining values to general-purpose or special-purpose registers.

3. Address generation does not serve the same purpose as the code-placement steps described later in in this series. Some instructions may use addressing modes that depend on properties of the addresses. For example, certain array-oriented instructions may work best at certain strides. Pre- or post-increment addressing can also be used to walk through the stack, providing data is put in the stack in the order in which it is used.

4. Instruction scheduling is important in pipelined and parallel machines. CPUs with branch delay slots must fill those slots with appropriate instructions. VLIW processors also require instruction scheduling.

Instruction modelling
Instruction modelling is key to the design of ASIP compilers. When designing specialised instructions, we also need to design compilers that can make use of those instructions. We cannot in general rely on compiler designers to create handcrafted compilers for ASIPs. For compilers to adapt automatically to new instructions, we must describe those instructions in ways that allow the compiler to generate code.

To understand the problems of instruction selection for complex processors, let us consider the basic problem formulation and an algorithm to solve it. We will use the twig code generator of Aho et al. [2] as an example, limiting ourselves to data flow operations.

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