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Understanding configurable IP and VHDL NULL range

Posted: 29 Aug 2013     Print Version  Bookmark and Share

Keywords:SoC designs  IP cores  configurability  VHDL  NULL range 

Let us consider the behaviour of a few commonly used synthesis tools (table 2).

For some of the synthesis tools mentioned, the NULL port is being removed, before completing the language semantics checks. Hence, during the language semantics checks, these tools error out. This means a designer has no way of using NULL port with these tools. If he explicitly connects the port there will be language error. On the other hand, if the ports are omitted, that is an error situation too.

 

Table 2: Behaviour of a few commonly used synthesis tools.

Recommendations
This study shows that the behaviour of different EDA tools is not consistent. If a designer plans to use a set of generics that would result in NULL range, he should ensure that the tools he uses support the behaviour that he is looking for. There are at least some synthesis tools which will not allow the flow to complete whichever way, if the port size turns out to be NULL range.

Synthesis tools are good in removing the NULL ports as well as the associated cone of logic. However, during component declaration and instantiation they should still allow the NULL port to be specified, as long as the NULL port is still connected to another NULL range signal.

Since different tools exercise some degree of special handling for NULL range signals, it is possible that some of the basic checks around NULL range might get missed by specific tools, as shown by Simulator-4. Hence, the designer should be extra careful to ensure that the following are always met, rather than depending on the tools to catch these, at least for NULL range:
 • Component declaration in the SoC should exactly match the entity declaration of the IP core.
 • The signals and ports being connected should have their range specified in terms of using the same set of expressions involving the same generics. This ensures that if a specific signal/port becomes NULL range, the connected signals/ports will also become NULL, thus avoiding size mismatch.

About the authors
Karthikeyan Subramaniyam is currently working as Senior Verification Engineer at Xilinx. Prior to this, he worked for Synopsys. He received BE in Electrical and Electronics from Coimbatore Institute of Technology in 2004. His areas of interests are in Simulation, Synthesis and PowerTools with strong HDL background. He has strong verification exposure with SystemVerilog, VMM & OVM.

Nithin Kumar Guggilla is currently working as Senior Verification Engineer at Xilinx. Prior to this he worked for Synplicity and Tejas Networks. He received MTech in Electronic Design and Technology from IISC, Bangalore in 2005. His areas of interests are in synthesis with strong HDL background.

Dhiraj Kumar Prasad is currently working as Verification Engineer at Xilinx. Prior to this he worked for Interra Systems and Cadence. He received BTech in Electronics and Instrumentation from WBUT University in 2006. His areas of interests are in simulation, synthesis and HDL languages.

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