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Adapter allows verification of PCIe 3.0 design

Posted: 31 Jul 2013     Print Version  Bookmark and Share

Keywords:Cadence Design Systems  SpeedBridge Adapter  PCIe 3.0  Cadence Palladium Verification Computing Platform 

Cadence Design Systems Inc. has introduced an adapter that the company said offers easy bring-up and fast debug of PCIe-based designs when used with a Cadence Palladium Verification Computing Platform, and is backwards compatible with PCIe 2.0-, 1.1- and 1.0a-based designs. The SpeedBridge Adapter for PCIe 3.0 reduces time to market and system risk for complex designs by providing high-speed interaction with real-world traffic in a pre-silicon environment running production-level software drivers and an OS, detailed the firm.

The SpeedBridge Adapter is designed for pre-silicon RTL and integration of PCIe-based ASICs and SoCs and allows system emulation under real-world operating conditions. The adapter verifies emulated PCIe 3.0 designs with the actual ASIC or SoC software and hardware, driver and application development, and runs with existing software and software test programmes or analyser.

"Increasingly, designers are faced with a difficult balancing act of managing increasing design complexities and shrinking time-to-market windows," said Christopher Tice, corporate VP, hardware system verification, system and software realisation group at Cadence. "PCIe 3.0 has increased complexity levels including higher data transfer rates (eight gigatransfers per second), backwards compatibility requirements and different standards for equalisation. In order to prevent costly re-spins and time-to-market delays, it is imperative for designers to perform complete system verification under complex real-world conditions with high fidelity full-speed interfaces."

The Cadence SpeedBridge Adapter for PCIe 3.0 is shipping.





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