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Interfacing protocol signals in SoC

Posted: 22 Jul 2013     Print Version  Bookmark and Share

Keywords:system on a chip  SoC  JTAG  Ethernet  DSPI 

Nowadays, a system on a chip (SoC) consists of several different microprocessor sub-systems, memories and support for I/O interfaces such as JTAG, Ethernet, DSPI, SENT etc for communication with the outside world (figure 1).

All these are universally accepted and have some timing requirements which may be in form of input/output delay requirements or special timing requirements (like transition and skew requirements for different signals), which need to be taken care of at the STA end. In this article, we will be focusing on one of these – maximum and minimum skew between two signals.

Some of these protocols (like DDR) have requirement for a finite maximum skew (difference in delays) between the various signals of a bus. All data has to change within a very small timing window. On the contrary, minimum skew requirement is generally specified to prevent the race condition between two signals. This is usually one sided; e.g. signal 'a' should follow 'b' after some finite time. Until recently, these skew requirements were modelled in a roundabout manner and had to be updated regularly which adversely impacted the STA analysis time of each database as there were multiple iterations for IO constraints maturity. Also, the constrained signals' timing may get deteriorated during optimisation in the absence of constraints on these signals. There can be different ways of implementing this using multiple command combinations. Each has its own merits and demerits. Let's look at three methods to achieve this purpose:
 • Applying minimum/maximum delay constraints on data signals
 • Modelling as input/output delays
 • Applying setup/hold checks considering one of the data signals as reference signal
 • Applying minimum/maximum delay constraints

Figure 1: SoC interfacing with the outside world through I/O protocols.

We can apply min and max delay constraints on data signals so that data changes only within a given window. This method can be used to constrain multiple signals for skew requirement as discussed below. We are essentially assuming these signals to have some characteristic delay range, which is a pure assumption or based on prior experience. The EDA command to apply min/max delay is:

set_min_delay/set_max_delay signal

A data bus can be constrained to be within a specific window by constraining each bit signal with min and max delays (where max_delay > min_delay) (figure 2).

Figure 2: Constraining signals to be within window by applying min/max delays.

set_min_delay data_bus[*]
set_max_delay data_bus[*]

The maximum skew requirement window will then be:

Max_skew_requirement = Max_delay_value – Min_delay_value

Similarly, the timing requirement for minimum skew can be justified by applying max_delay constraint to one signal (the one which is to occur first) and min_delay constraint to the other (the one which is to occur later [figure 3]).

Figure 3: Constraining signals for minimum skew by applying min/max delay constraints.

set_max_delay signal_1
set_min_delay signal_2

Where:

Min_skew_requirement = Min_delay_value – Max_delay_value

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