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Boost efficiency of embedded encryption apps

Posted: 12 Jul 2013     Print Version  Bookmark and Share

Keywords:Advanced Encryption Standard  microcontroller  AES-128  CPU  FIFO 

The CPU can only perform 8bit operations and cannot keep the whole block in its view. Effectively, row shifting is essentially changing the location of a byte. For example, after row shifting, byte S1,0 takes the place of S1,3. Thus, DMA can prove to be much more efficient in picking a byte from one address and transferring it to another.

Column mixing
After row shifting, column mixing is the next step. AES column mixing involves transformation of the data block such that a whole column (4B) is processed to generate a byte. The transformation is effectively multiplication in GF(28) with the polynomial p(x)=x8 + x4 + x3 + x + 1. The matrix representation of column mixing is shown in figure 4.

Figure 4: Column mixing.

Mathematically, a byte A is generated from a,b,c, and d according to the following equation:

Implementation of multiplication in hardware has always been a challenging task, which is the reason why this equation is generally not implemented in this form. According to the book, Cryptography and Network Security, multiplication of a value by x (i.e. by 02) can be implemented as a 1bit left shift followed by a conditional bitwise XOR with 0x1B (00011011), if the left-most bit of the original value (before the shift) is 1. By this rule, the above equation simplifies to

where "check_msb" returns 0x1B if the MSB of the byte is 1 and returns 0x0 if the MSB is 0. This simple manipulation can greatly reduce the hardware resource consumption for column mixing.

An SoC with a programmable architecture can implement this process efficiently in hardware. For example, with the PSoC architecture from Cypress, Universal Digital Blocks (UDBs) serve as an ideal candidate for implementing the column mixing operation. Figure 5 shows the UDBs architecture from the PSoC Technical Reference Manual (TRM):

Figure 5: PSoC's Universal Digital Blocks (UDBs).

It can be seen that all of the above mentioned byte-wide operations (shift by one bit, XORing) can be performed in a Data Path in a single clock cycle. Before moving on to the actual implementation on UDBs, it is important to understand the internal structure of the Data Path.

A data path in UDB is comprised of two 4B deep FIFOs, two data registers, two accumulator registers and an 8bit wide ALU. These hardware resources can be made to operate with the help of a state machine. These 8 present states can be configured with the help of Data Path Configuration tool. Figure 6 from PSoC's TRM shows the Data Path:

Figure 6: Data path in PSoC's UDBs.

Figure 7 shows a state machine for implementation of Equation iii (Column Mixing operation) using UDBs:

Figure 7: State machine for column mixing usings UDBs.


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