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Pre-CTS clock path timing analysis, automation

Posted: 08 May 2013     Print Version  Bookmark and Share

Keywords:VLSI  timing closure  clock tree synthesis 

Shown in figure 1 is a typical primitive clocking structure. It will, when passed to the procedure we developed, will produce output as follows. Here, L1, L2 etc. are indicative of number of clock gatings/dividers between the root source and the divider/clock gating under consideration. H1, H2 etc. are the hierarchies that are being driven through each clock gating/divider. The number of flops being driven through each level is also mentioned alongside.

Exploring clocking structure by analysing the reports in textual format is very simple and involves less effort from the designer side compared to tracing in GUI. In figure 2, we show the flowchart for the procedure that we followed to achieve the above output.

Figure 2: Procedure for clock tree tracing. (Click on image to enlarge.)

Finding potential clock sources
The approach given above works only when you know all the clock sources in advance. But, sometimes, it is not possible to know the clock sources upright i.e. clocking information is not given in the architecture document. Eg. One might be working on a hierarchical design and all the clock sources might be at top level. For the block, we may consider root sources as the block ports themselves. So, while developing constraints for a block, there is no straight method to have known the clock sources upfront. Conventional approach, in such cases, involves picking an unclocked flop from timing lint reports, tracing the fanin cone of its clock pin to reach a probable clock port and defining the clock there. This is repeatedly done until timing lint report is clean with respect to unclocked flops. Much of the time can be saved if we follow the straightforward approach to find all the ports/divider pins in fanin of all sequential clock pins, filter them out for the probable cases of clock definitions and defining clocks there. We developed a procedure to do just the same. Doing so also returns clock controlling signals (functional or DFT eg scan mode etc). We may easily filter these, as is usually clear with their names, to get actual clock ports. Given below is a sample report that was generated as an output from the procedure. Looking at the sample output report, it is quite easy to filter out the clock ports as the names say it all. The last four signal ports are clock enable signals.

Figure 3 shows the procedure that we followed to achieve the output as desired.

Figure 3: Procedure to find clock ports for a block.

Finding broken clock paths
Once the designer is into defining clocks, as part of the constraints, one issue that often comes up is that of broken clock paths. This is usually reported in the timing lint reports as "master clock edge not reaching the generated clock", "A latency path from the 'Rise/Fall' edge of the master clock at source pin to the 'Rise/Fall' edge of generated clock cannot be found" or "clock not found where clock is expected". The two major reasons for this kind of problems are 'wrong case application in constraints' and 'the broken circuit' where there exists no logical or structural connection 'between master and the generated clock nodes' or 'between clock source and clock sink'. Logical, for instance, may mean the generated point cannot be traced through the connecting logic to produce the desired waveform (e.g generation of 50% duty cycle waveform is not possible through a clock gating cell or inverted generated clock is not possible if there is no inversion element present in the connecting path). Structurally broken paths, on the other hand, are the ones where there is actually no electrical connection between the master and generated nodes.

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