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EDA/IP  

Pre-CTS clock path timing analysis, automation

Posted: 08 May 2013     Print Version  Bookmark and Share

Keywords:VLSI  timing closure  clock tree synthesis 

More practical approach is to configure EDA tool for optimistic CRPR setting so that it considers POINT 1 CRPR. For this, we have to be sure that none of the reconvergence is intentional and all cases are due to mode merging only. So, for this, first we have to identify all the clock reconvergence cases and get them reviewed from the IP owners/design team. We chose the second way as it is convenient in approach and involves less effort from analysis point of view. We developed a procedure to identify the reconvergence cases in design. We present below the format of the report generated by the procedure we developed. The path taken by launch clock is shown in violet and that by capture clock is in brown.

Figure 7: A possible pictorial representation for reconvergence case 1.

Figure 8 shows the steps that we used to report reconvergence cases in the design.

Figure 8: Flowchart for procedure to find clock reconvergence cases. (Click on image to enlarge.)

These were few important pre-CTS clock path analysis techniques which help the backend designers immensely. So as evident, the vendor tools would normally not have much debugging/analysis capabilities but such algorithms can always be devised and implemented with the help of native tool command sets. These techniques finally help faster implementation closure and let designers have more breathing time to be spent on other designs issues.

About the authors
Vijay Bhargava is Lead Design Engineer at Freescale Semiconductors, Noida. In his career spanning 11 years, Vijay Bhargava has worked extensively on verification, digital IP, power estimation/modelling and DSP architectures. He has handled synthesis/APR and STA activities for SoC physical design.

Gourav Kapoor is Design Engineer at Freescale Semiconductors, Noida. He has been holding the said position for two years. He is part of the physical design team and responsible for constraints development and timing closure. He has been involved in both chip-level and block-level timing closure for various SoCs at 65nm and 45nm.

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