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ARM, Cadence deliver high-performing processor on 16nm FinFET

Posted: 16 Apr 2013     Print Version  Bookmark and Share

Keywords:Cortex-A57  processor  ARMv8 architecture  16nm FinFET 

ARM Ltd and Cadence Design Systems have revealed their successful partnership in delivering what they claim as the first ARM Cortex-A57 processor on TSMC's 16nm FinFET manufacturing process.

The test chip was implemented using the Cadence Virtuoso custom design platform, the complete Cadence RTL-to-signoff flow, ARM Artisan standard cell libraries, and TSMC's memory macro.

According to the companies', the Cortex-A57 processor is ARM's highest-performing processor to date, and is based on the new ARMv8 architecture, designed for computing, networking and mobile applications that require high performance at a low-power budget.

Cadence and ARM noted that TSMC's 16nm FinFET technology is a significant breakthrough that enables continued scaling of process technology to feature sizes below 20nm. The test chip, developed with Cadence's custom, digital and signoff solutions for FinFET process technology, was a collaboration that resulted in several innovations and co-optimisations between manufacturing process, design IP, and design tools, the companies said.

"More than ever, success at the leading edge of innovation requires deep collaboration. When designing SoCs incorporating advanced processors, like the Cortex-A57, and optimising the implementation using physical IP created for FinFET processes, the expertise of our partners is needed," said Tom Cronk, executive vice president and general manager, processor division at ARM. "Our joint innovations will enable our customers to accelerate their product development cycles and take advantage of leading-edge processes and IP."

The 16nm process using FinFET technology presented new challenges that required significant new development in the design tools. New design rules, RC extraction for 3D transistors, increased complexity of resistance models for interconnect and vias, quantised cell libraries, library characterisation that supports new transistor models and double patterning across more layers are some of the challenges that have been addressed in Cadence's custom, digital and signoff products.

"This major milestone was challenging on all fronts, requiring engineers from ARM, Cadence and TSMC to work as a unified team," said Chi-Ping Hsu, senior vice president of R&D for the silicon realisation group at Cadence. "Our combined efforts and commitment to innovation will enable our customers to adopt the next generation of IP, process and design technology for designing high performance, low-power SoCs."





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