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Boost yield using lithography friendly design

Posted: 09 Apr 2013     Print Version  Bookmark and Share

Keywords:Lithography Friendly Design  Resolution Enhancement Techniques  Optical Proximity Correction 

Bridging failure: If the PV band of a target pattern lies outside the outer tolerance band then bridging occurs. This is because the spacing between the PV bands of the adjacent target patterns may become less than the minimum LFD spacing. A bridging failure can be detected by overlapping the PV band of the target pattern with the outer tolerance band and it exposes locations (on the PV band) that lie outside the outer tolerance band, which indicate bridging hotspots. Due to bridging, the PV-band for one feature overlaps or comes very near the PV-band of another feature which may result in shorts. This failure is shown in figure 3.

Figure 3: Bridging failure.

Figure 4: Images of pinching and bridging during manufacturing.

Figure 5: Area overlap failure.

Area overlap failure: If the overlapping area between the PV bands of two overlapping target geometries is less than the minimum LFD overlap area then area overlap failure occurs. The minimum LFD overlap area is similar to the minimum enclosed area DRC rule. It is the minimum area enclosed by the overlapping PV bands of the two target layers so that manufacturing failure does not occur. Figure 5 represents area overlap failure in which overlapping area between the PV bands of two layers Layer 1 and Layer 2 is less than the minimum LFD overlap area. This failure can be fixed by increasing the size of the cut between layer1 and layer2.

About the authors
Vishant Gotra is a Design Engineer at Freescale Semiconductor, India Pvt Ltd. He is mainly responsible for SoC Physical design activities. Physical verification activities and IR drop analysis (Static/Dynamic) are his main expertise and focus areas.

Rishabh Agarwal is a Design Engineer at Freescale Semiconductor, India Pvt Ltd. He is mainly responsible for SoC Physical design activities. Analogue Routing, Floorplanning and IR drop analysis (Static/Dynamic) are his main expertise and focus areas.

Gurinder Singh Baghriaÿis a Design Engineer at Freescale Semiconductor, India Pvt Ltd. He is mainly responsible for SoC Physical design activities. Floorplanning, power planning/estimation and IR drop analysis (Static/Dynamic) are his main expertise and focus areas.

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