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Enable peaceful coexistence of MicroBlaze, Zynq

Posted: 08 Apr 2013     Print Version  Bookmark and Share

Keywords:SoC  programmable logic  PCIe  RAM 

In addition, there are four channels of high-performance (64bit-wide) AXI attachment points. All four of these channels are slaves from the PS' perspective and are connected to the memory interface sub-system within the PS (figure 3). The purpose of these four channels is to allow masters in the PL to initiate double-data-rate (DDR) memory transactions.

This memory interconnect and DDR memory controller are the gateways to the DDR memory from all sources. While the Cortex-A9 processors usually have priority over the slave AXI connections, each one of the four slave AXI connections has a "service me now" signal that gives priority to the requesting channel. When this signal is not asserted, the architecture uses a round-robin scheme to determine which requestor can gain access to the specific type of memory.

Figure 3: Simplified connections to the DDR memory controller and on-chip memory (OCM).

The Accelerator Coherency Port (ACP) is another 32bit AXI PS slave connection from the PL. What makes the ACP unique is that it is tied directly into the snoop control unit (SCU). The job of the SCU is to ensure coherency among the L1, L2 and DDR memories. Using the ACP, you can access the fast cache memory for each of the Cortex-A9 processors in the PS and not be concerned with synchronising data with the main memory (as the hardware will automatically take care of this). This capability greatly reduces the burden of design and provides a significantly faster way of moving data between the processors and the PL.

Beyond AXI links, the Extended Multiplexed Input and Output (EMIO) signals are available for routing many of the PS' hard peripherals through the PL to access the package pins. There are only 54 package pins tied directly to the PS; however, the PS' hard peripherals can use considerably more than these 54 pins. The EMIO is the conduit between the PS' hard peripherals and the PL. These I/O signals can be routed directly to the package pins available to the PL. Alternatively, you may use them to communicate with a compatible peripheral located in the PL.

Another variety of miscellaneous signals between the PS and PL falls into five basic categories: clocks and resets; interrupt signals; event signals; idle AXI; DDR memory signals; and DMA signals.

 • Clocks and resets: There are four independent programmable frequencies that the PS makes available to the PL. Typically one of these clocks is used for the AXI connections. Each of these clock domains has its own domain reset signals for resetting any device associated with that domain.
 • Interrupt signals: The general interrupt controller (GIC) in the PS collects interrupts from all available sources, including all of the interrupt sources from the PS' peripherals and 16 "peripheral" type interrupts from the programmable logic. Additionally, there are four direct interrupts that tie to the CPUs (IRQ0, IRQ1, FIQ0 and FIQ1). A total of 28 interrupts (from the PS' peripherals) are available to the PL.
 • Event signals: These "out-of-band" asynchronous signals indicate a special condition of the PS. The PS provides a number of signals that indicate which CPU has entered a standby mode and which CPU has executed a SEV ("send event") instruction. The PS can leverage an event signal to wake from a WFE ("wait for event") state.
 • Idle AXI and DDR memory signals: The idle AXI signal to the PS is used to indicate that there are no outstanding AXI transactions in the PL. Driven by the PL, this signal is one of the conditions used to initiate a PS bus clock shutdown by ensuring that all PL bus devices are idle. The DDR urgent/arb signal is used to indicate a critical memory-starvation situation to the DDR arbitration for the four AXI ports of the PS DDR memory controller.
 • DMA signals: The direct-memory-access module within the PS communicates with the PL slaves via a series of request-and-acknowledge signals.

Accessing DDR memory
Let's take a look at an example design that covers several common needs the typical MicroBlaze user might have, including how to access DDR memory, how to use the peripherals in the PS' IOP, how to pass blocks of data between the MicroBlaze and the PS, and how to synchronise events between the MicroBlaze and the PS. Figure 4 shows specific techniques to address each of these issues (labelled 1-4, respectively).

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