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Guide to early power analysis

Posted: 27 Feb 2013     Print Version  Bookmark and Share

Keywords:system-on-a-chip  register transfer level  simulation 

The power for the memory varies significantly based on the different "when" conditions in the library model. So even if we get an accurate toggle rate and duty cycle of all the nets in the design, no simulation output will provide the duty cycle of these "when" conditions. This is because these "when" conditions are not present as nets in the design. So even if you have a very detailed VCD file for the design, to accurately calculate power, the power analysis needs to do an internal cycle-based simulation.

Adopting a hybrid approach
It is clearly evident that doing a cycle-based evaluation for each condition of the power table for each cell in a design is not a scalable solution for large SoCs. So instead of taking a purely probabilistic approach, or a complete cycle-based approach, power analysis flows can take a hybrid approach depending on the following factors:

 • Stage of the design, including availability of the RTL or netlist, or libraries for hard macro
 • Availability of simulation data
 • Design specific data – like memory, datapath, analogue cells, black boxes, etc.

Figure 1: A typical early stage IP sub-system block.

Suppose we have a design at an early stage of RTL coding. As shown in figure 1, there are 4 blocks:

Block A: This is an RTL block for which simulation data is available.

Block B: This is an RTL block for which no simulation data is available so far.

Block C: This is a black box for which the RTL is still not available, but the designer is aware of some characteristics of this block.

Block D: This is block primarily consisting of memories and we have a simulation output file for this block.

As we can see, there is a fair variation in the progress and the characteristics of each block. Also, each block is at a different stage with respect to the availability of simulation data. So the early power analysis flow should be able to handle the best information available.

Block A has RTL with simulation data information. So the power analysis tool should be able to accept a simulation file at the block level. Since this block is mostly standard cell logic, power analysis tools will consume a VCD or FSDB data and convert it into toggle counts and duty cycles for each net. This will ensure that power estimation is much faster than a cycle-based approach. The error introduced here because of the loss of spatial and temporal correlation will not affect the accuracy of results for this kind of a design.

Block B is also an early stage RTL design where the simulation data is still not available. But at this stage, the designer has some information regarding the critical signals. These will be clocks and control signals.

Here, we can specify the clock period of the clock and the activity information or toggle rate for critical signals.

Many times, it is hard to specify the toggle rate for a signal internal to the design. However, even for vector-less power estimation, capturing the information for such signals is important. So the flow should allow specifying toggle information on such signals. One such signal is clock gating enables for blocks or registers.

Block C is a black box. There is no RTL information. So for such a case, the flow should be able to capture coarse design information, as shown below, in an early power analysis tool such as Atrenta's SpyGlass Power:

blackbox_power -instname block_c -equiv_nand2_count 3000 \

-register_count 100 –activity 0.3 -clocks a1 a2 -clock_percentage 0.5 0.5
The above command in the power analysis tool specifies that the black box will contain 3,000 NAND gate equivalent cells and 100 registers. Also, the average activity of this module will be 0.3. With this information and technology libraries the flow can estimate the power of this black box.

Block D contains many memories. Earlier in this section, we have seen that memories have a very high variation of dynamic power based on different access operations like "read" and "write". So for this block, we need very accurate power estimation. A robust power estimation flow should be able to identify such logic from other logic in the design. Once it identifies such cells, it will enable very accurate tracing of each "when" condition for the cells. This is time-consuming, but the key is to be able to identify a critical number of cells that will benefit most from such detailed cycle-based evaluation.

The power analysis flow should be able to consume these different types of activity information and apply them based on design knowledge to estimate the power at an early stage in the design.

Guideline 2: Learn from existing netlist design and apply it to the new RTL
One of the key benefits of RTL power estimation is to get the power analysis early in the cycle. The flow does not go through the complete back-end steps. However, a good power analysis flow should be able to capture the intent of back-end analysis and apply it to the RTL. Scavenging an existing prototype design netlist can provide good information to RTL analysis tools for accurate power estimation as shown in figure 2.

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