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Hardware in the loop simulation for Zynq-7000 SoC

Posted: 14 Jan 2013     Print Version  Bookmark and Share

Keywords:simulation model  FPGA logic  RTL  processor 

The Zynq-7000 All Programmable SoC does not deliver a simulation model which poses a problem for designers. This application note describes a method/solution to bring the MPCore processor sub-system (PS) within the ISEDesign Suite Simulator (ISim) simulation environment with the help of Zynq-7000 platform Hardware In The Loop (HIL) simulation technology.

The Zynq-7000 All Programmable SoC (AP SoC) is a new class of product from Xilinx, which combines an industry-standard ARMdual-core Cortex-A9 MPCore processor sub-system (PS) with Xilinx 28 nm programmable logic (PL). Traditionally, Xilinx offered the MicroBlaze embedded processor. Peripheral IP in the FPGA logic was created in RTL and the entire system was simulated using an RTL simulator in which the simulation RTL model for the MicroBlaze processor was provided by Xilinx.

Zynq-7000 AP SoC HIL technology is a technique that simulates, debugs, and tests both the PS and the PL portions of a Zynq-7000 AP SoC design. All of the AXI-based IP connected to the PS through the master/slave general purpose (GP), high performance (HP), or auxiliary coherency port (ACP) can be simulated in ISim, while the PS is simulated in the hardware (the ZC702 board). The AXI-based PL interfaces are clocked using the testbench clock, allowing cycle accurate simulation of IP in the PL. The PS and the DDR memory operate in free-running mode. This approach is very useful for developing IP with the PS and also for IP driver development and software debugging. The software support for Zynq-7000 AP SoC HIL is released in the 14.2 version of the Xilinx ISE design tools.

View the PDF document for more information.

Originally published by Xilinx Inc. at www.xilinx.com as "Hardware In The Loop (HIL) Simulation for the Zynq-7000 All Programmable SoC"





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