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Unravelling the truth about analogue IP at 28 nm

Posted: 18 Dec 2012     Print Version  Bookmark and Share

Keywords:system-on-chip  Register transfer logic  IP 

The economics of system-on-chip development are objective and well understood. Industry-wide trends set the stage for integrating more functions into a SoC, which then drives the scaling down of process technology nodes. In the resulting product, all of the previous product's functionality is implemented while more functional blocks are added to build increasingly complex functionality. This trend is not questioned—it is an axiom.

Register transfer logic (RTL) is agnostic to the process technology node, so porting digital functionality is not perceived as problematic. However, analogue functionality is perceived as more challenging because of its closer dependency on the process characteristics. At each new node, the debate regarding whether or not to integrate analogue IP into the SoC is rekindled until the economics validate the integration. Successful mixed-signal SoCs in all previous process technology nodes have demonstrated this cycle despite the persistence of three myths around the economics of analogue block implementation in advanced process technologies.

These three myths deserve to be analysed to better understand why they are erroneous.

Myth #1: The economics of analogue integration don't add up
Analogue circuitry does not scale in the same way as digital circuitry. The performance requirements for analogue blocks, especially in terms of linearity, mean the function is easier to implement using thick oxide devices at I/O supply level. As this type of device has not changed in many generations, the total area of the analogue block that uses it is also more or less constant.

In this case, the myth is that the relative portion of the real estate allocated for the same function in new process technologies keeps increasing, and therefore the cost also increases to a point where integrating the analogue function is no longer justified.

Advances in analogue circuit techniques disprove this myth. For example, digitally assisted analogue architectures, digitally calibrated architectures, and other dithering and randomisation techniques can, through digital processing, eliminate most of the non-idealities inherent to deep-sub-micron devices. This simplifies the circuit, making it more robust and increasing performance while using only thin-oxide devices.

By reducing analogue complexity and taking full advantage of process characteristics, the economics of integration are positive to analogue block integration. Most designers find that integrating these blocks end up improving their competitive position in the market.

Myth #2: Integrating analogue IP is too risky
Given the huge costs for developing new products at advanced process technology nodes, risk mitigation is a very important factor to consider when deciding what approach to use. Analogue blocks are often judged to be too immature and risky for integration in new process technologies.

Advanced process technology nodes pose new challenges to the development of integrated circuits. In particular, some performance characteristics of analogue blocks rely on specific process characteristics. For example, device matching and output impedance suffer larger variations due to layout-dependent effects such as well proximity effect (WPE) and shallow trench isolation (STI) stress. These and other ageing effects are prevalent on advanced process technology nodes and can degrade circuit performance. All of these effects must be taken into account during the architecture and design phases.

However, digitally assisted analogue architectures alleviate the performance issues and make these blocks less sensitive to process effects. In addition, thorough design validation flows ensure that all effects are accounted for during the design phase.

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