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Boost efficiency of photovoltaic systems

Posted: 07 Dec 2012     Print Version  Bookmark and Share

Keywords:Photovoltaic  inverter system  customisable system-on-chip  FPGA 

One last technique for improving efficiency is to use power factor correction (PFC). Capacitive and inductive loads cause a poor power factor, which is the ratio of real power to reactive power where real power is useful and reactive power is wasted (the result of current and voltage being out of phase). With a power factor of one, the voltage and current are in phase, which provides maximum power. By actively correcting the power factor, designers can, in effect, improve system efficiency.

The FPGA option
Although PV inverters have traditionally been implemented using a variety of processors including microcontrollers and digital signal processors (DSPs), a third option is to include programmable logic in the solution. This is possible using field programmable gate array (FPGA) technology, which enables customised controllers to take advantage of ongoing cost, performance, flexibility and gate capacity improvements. FPGA technology has reached the point where it can now outperform microcontrollers, DSPs and ASICs at the same price range.

FPGA technology provides particularly compelling benefits when there is the demand for highly optimised solutions with special algorithmic functions such as PWM, MPPT and PFC implementation. In these cases, FPGAs provide a very low-cost hardware and software customisation platform. To further improve flexibility, designers can opt for flash-based FPGAs that can be reprogrammed at any time, thus reducing development costs while permitting field upgrades and bug fixes.

Another option is the customisable system-on-chip (cSoC), which combines programmable logic with an embedded controller and configurable analogue. cSoC technology offers many options for further enhancing the design and performance of a PV inverter system. The integration of board-level components into a single monolithic IC reduces cost and power dissipation. Plus, because there is no board-level wiring, there are shorter circuit delays. Eliminating the long wires that are otherwise needed to connect devices on the board also enables designers to avoid parasitic ringing, oscillations and other associated problems, as well.

cSoCs also give designers the flexibility to implement control functions in hardware, software, or a combination of both. Plus, the cSoC's programmable analogue can be used to monitor and evaluate operating conditions, giving end-users and utilities critically important visibility into potential failures before they occur so they can take pre-emptive actions. Finally, the highly parallel nature of the cSoC's programmable fabric enables arithmetic co-processing. By using hardware acceleration techniques, cSoCs increase computational throughput. They can implement any required DSP functions that cannot be feasibly implemented in the embedded microcontroller. Whenever a signal processing function is required, the embedded microprocessor makes calls to a coprocessor that has been constructed in the cSoC's programmable logic core. This offloads the microprocessor while delivering the needed throughput. System designers can choose from a number of off-the-shelf IP cores that greatly simplify the task of implementing DSP algorithms in hardware for PV system applications.

As demand grows for more efficient and reliable PV systems, system designers have a number of options to consider. The inclusion of programmable logic in today's PV module solutions offers opportunities to improve system cost and performance ratios while adding valuable new features and capabilities.

About the author
Rufino Olay is an Industrial Business Manager at Microsemi Corp., responsible for alternative-energy-focused designs and applications. His expertise includes business development, P&L responsibilities, NPI, and production launches for the FPGA-, PV-, and wireless-infrastructure industries. Olay holds a bachelor of science in electrical engineering from San Jose State University.

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