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Design suite speeds implementation from C, RTL

Posted: 01 Aug 2012     Print Version  Bookmark and Share

Keywords:IDE  Design suite  tools 

Xilinx Inc. releases the Vivado Design Suite 2012.2 at no additional cost to ISE Design Suite customers who are currently in warranty. This software is the first in a two-phase rollout, with the first phase focused on accelerating time to implementation from C and RTL, and the second focused on accelerating time to integration of system-level functions.

Vivado Design Suite 2012.2 is said to deliver a highly-integrated design environment with a new generation of system-to-IC tools that include High-Level Synthesis, RTL Synthesis with the industry's best SystemVerilog support, revolutionary analytical place and route, and an advanced SDC-based timing engine so developers can increase their productivity with a 4x acceleration in design implementation.

Given the size and complexity of today's designs, developers face multi-dimensional design challenges that prevent them from achieving automated design closure. The Vivado Design Suite 2012.2 place and route technology accelerates implementation cycles by using analytical techniques to optimise for multiple and concurrent design metrics, such as congestion, total wire length and timing. For complex designs, this results in performance improvements of 15 per cent corresponding to a one speed grade advantage over the ISE Design Suite. The same performance improvement also extends Xilinx's high-performance leadership over competing devices by three speed grades among the mid-range families, while delivering better performance vs. power trade-offs on the high-end, and better performance on the low-cost end of the respective product portfolios.

Free tools
The Vivado Design Suite also includes the Vivado High-Level Synthesis (HLS) for All Programmable 7 series FPGA and Zynq-7000 EPP SoC devices. Vivado HLS will be included at no additional cost to ISE Design Suite DSP Edition and System Edition customers currently in warranty. Designers can quickly explore implementation architectures for complex algorithms by synthesising their C, C++ or System C code to RTL. Vivado HLS also integrates with the System Generator tool by creating fast simulation models for enabling the rapid development of applications such as video, imaging, RADAR and base band radios. Not only does Vivado HLS accelerate algorithm implementation, it also reduces verification time by up to 10,000x while improving system performance by enabling RTL micro-architecture exploration.

In warranty ISE Design Suite Logic Edition and Embedded Edition customers will receive the new Vivado Design Suite Edition, and those with ISE Design Suite DSP and System Edition will receive the new Vivado Design Suite System Edition at no additional cost.

The new features and methodologies for accelerating time to integration will be available early next year as part of the second phase of the Vivado Design Suite rollout. Please visit Xilinx.com to download

The latest version of the ISE Design Suite and Vivado Design Suite can be downloaded . Customers can also sign up for Vivado Design Suite training classes.





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