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Gigabit serial links enable multi-core scalability

Posted: 20 Jun 2012     Print Version  Bookmark and Share

Keywords:multi-core processors  serialiser/deserialiser  SATA 

As an increasing number of high-performance, data-intensive applications—such as wireless basestations and high-performance compute platforms—benefit from multi-core processors, system scalability can only be achieved through high-capacity embedded interconnect. Gigabit serial links help enable system scalability by reducing system cost, area footprint and pin count while delivering greater parallelism, performance and capacity.

Gigabit serial links define the physical layer of the high-speed communication link. The serialiser/deserialiser (serdes) at the heart of the gigabit serial link transforms the parallel data inside the device into serial data streams for communication to the external world. Compared with parallel interfaces, serdes-enabled serial links shrink the device area and package size while reducing cost and power consumption, enabling higher system performance.

Figure 1 offers a high-level overview of serdes operation. In the transmit direction, the byte serialiser converts parallel bits into serial bytes, then encodes them before sending them out to the serial links.

The most common encoding scheme is 8b/10b, which maps 8bit data bytes to 10bit code by adding clock and framing control information so the receiver can recover that information and align it with the transmit data.

In some cases—such as for 10-, 40 and 100-Gbit/second Ethernet—64b/66b encoding is used to enable increased data payload throughput.

In the receive direction, the serial input is first decoded by an 8b/10b or 64b/66b decoder. It then is fed into a clock and data recovery (CDR) block to synchronise with the transmit clock and framing before being sent to the deserialiser for conversion to parallel data for internal processing.

Figure 1: The serialiser/deserialiser is the foundation of gigabit serial links.

Many communications protocols can be built on top of the serdes function for various data-intensive applications. Figure 2 shows a typical system-on-chip integrating the CPU and digital signal processor, as well as hardware accelerators for application processing. Gigabit interconnects that can be built on top of the serdes function include Gigabit Ethernet, Common Public Radio Interface/Open Base Station Architecture Initiative (CPRI/OBSAI), JESD204B, Serial RapidIO and PCI Express (PCIe).

Figure 2: Communications protocols can be built on top of the serdes function in data-intensive applications.

These interconnects greatly enrich SoCs for today's high-performance computation needs.

The options in detail
Gigabit Ethernet is a widely adopted data link layer for wired data communications. The standard's interface rate is being increased to meet bandwidth requirements from 1 Gbit/s to 10, 40 and 100 Gbit/s. 10G Ethernet has become popular in recent years and can connect to various physical layers (PHYs) through optical fibre or copper physical media.

In 2010, the IEEE802.3ba standard was established to support 40G and 100G Ethernet; here, either four or 10 lanes with 10- or 25-Gbit/s respective signalling are used to achieve a 40- or 100-Gbit/s respective data rate.

Gigabit Ethernet can be used as a backup connection for either short- or long-reach data transport, as it delivers packet-based non-real-time data for applications that can tolerate the communication latencies. Latency can be reduced in certain cases through cut-through operations in Layer 2 switches, where data packets can be forwarded as soon as the destination MAC address is received.

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