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Cadence aids ST's 20nm SoC test chip tape-out

Posted: 04 Jun 2012     Print Version  Bookmark and Share

Keywords:SoC  test chip  mixed-signal  design flow 

Cadence Design Systems Inc. announced that it has helped STMicroelectronics' 20nm test chip tape-out. This tape-out marks an industry milestone for Cadence in delivering an end-to-end mixed-signal design flow for 20nm.

Engineers from the two companies are said to have collaborated closely to develop technologies and deploy methodologies using the Cadence Encounter and Virtuoso platforms to enable design, implementation and signoff, in addition to development of foundational IP and a SKILL-based process design kit (PDK) for the 20nm process.

As part of this collaboration, STMicroelectronics has deployed the full Cadence 20nm flow, physical IP libraries and the related PDK.

"Working together over the past two years, Cadence and STMicroelectronics successfully deployed an efficient methodology and design automation to address the requirements for designing complex mixed-signal SoCs," said Chi-Ping Hsu, senior vice president, research and development, Silicon Realisation Group at Cadence.

ST performed automated layout generation using Cadence Virtuoso Layout Suite into STMicroelectronics' custom IP design development, including foundation IP, PLL and video DAC. Designers used a 20nm PDK that enables advanced capability such as Modgens, constraints and space-based routing. The Encounter Digital Implementation (EDI) System provided 20nm physical implementation capabilities for the tape-out, handling 20nm process requirements during placement and optimisation as well as routing.





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