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Cadence updates DDR PHY interface IP

Posted: 31 May 2012     Print Version  Bookmark and Share

Keywords:DDR  PHY  interface  IP 

Cadence Design Systems Inc. adds support for the latest release of the DFI specification, version 3.1 to its comprehensive suite of DDR controller and DDR PHY design IP as well as its Cadence Verification IP Catalog.

The new version adds support for the LPDDR3 mobile memory standard for smartphones and tablets, and includes enhancements to the PHY's low-power interface and training features.

"As the performance of the processors used in today's consumer electronics devices improves, so does their need for higher-bandwidth memory. The DFI interface standard was developed to give SoC designers a way to easily incorporate high-performance memory into their SoCs," said Marc Greenberg, director of marketing, SoC Realisation, Cadence.

Cadence claims over 400 design wins for DDR controllers and PHYs, and all DDR3 designs currently in development use the DFI interface. With the addition of support for LPDDR3 memory, the DFI standard can now be used in the development of SoCs targeting smartphone and tablet applications that require higher-bandwidth memory. The standard has been recognised by JEDEC, the microelectronics industry's open standards organisation.

DFI 3.1 is a memory interface standard that enables the interoperability of IP between different companies. It defines methods for interfacing to DDR4 devices (with data rates up to 3.2Gbps per pin) and LPDDR3 devices (with data rates up 6.4Gbps. and 12.8Gbps for a dual channel configuration). The preliminary specification is available now for download at www.ddr-phy.org.





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