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Utilise hierarchical methods for power intent specification

Posted: 17 May 2012     Print Version  Bookmark and Share

Keywords:power intent  hierarchical design  macro modelling 

This article first shows how to express power intent top-down in a hierarchical design, which allows the designer to set rules abstractly without worrying about the details of all the power domain crossings lower in the design hierarchy. The article then describes the concept of macro modelling to capture power intent for IP blocks. Next, it illustrates a bottom-up hierarchical approach that enables the designer to integrate the same block in multiple situations that require different uses of the block's internal power intent capabilities. Finally, the article describes how to use virtual ports and virtual power domains to simplify specification of rules for design objects that will later appear lower in the hierarchy, as the design implementation is refined.

Although the Common Power Format (CPF) is used as the main format to illustrate these capabilities, not all of these hierarchical capabilities are truly unique to CPF. The hierarchy support currently provided in the IEEE 1801 standard, Unified Power Format (UPF) 2.0, is also covered. The article concludes by reviewing recent developments towards methodology convergence between the Silicon Integration Initiative Low Power Coalition, which is responsible for CPF, and IEEE P1801.

Need for hierarchical low-power design
Semiconductor companies today are able to produce integrated circuits (ICs) of unprecedented scale, with tens to hundreds of millions of transistors on a single die becoming commonplace. This complexity, enabled by rapidly shrinking process geometries, which relentlessly continue to obey Moore's Law, is a double-edged sword. It allows unprecedented integration of circuits, enabling many different functions to be integrated in a single system on chip (SoC). But it also produces leakier transistors, driving the need for low-power design techniques (such as power shutoff or power gating) that specifically address leakage power.

Complex SoCs are designed hierarchically, with many different low-level functions integrated together into sub-systems, which in turn are integrated onto the SoC. Therefore, a good low-power design flow must not only automate low-power design, verification, and implementation—it must also support a hierarchical design methodology. In practice, hierarchical design is almost always a combination of top-down specification and bottom-up integration, with partitioning of design tasks, some of which are designed from scratch and others are provided by reused IP blocks in the form of hard or soft design macros. The blocks are integrated and verified bottom-up, but along the way, the designer must validate that the integrated design (the result of the bottom-up integration) fully meets the system specification. Thus, functional design and verification for these SoCs tend to be iterative, working both top-down and bottom-up to divide and conquer the massive quantity of details, while maintaining a clear view of the whole SoC.

The same approach works for power intent specification too. The low-power architecture, consisting of power domains, their states, and the resultant power modes, follows from the top-level system functionality and architecture, and is specified top-down early in the process. However, to be able to design leaf-level functions and integrate IP blocks that fit into this architecture, and to verify them, we must also have a hierarchical understanding of power intent. The following sections show how to describe and use power intent for top-down design, IP blocks and macros, and bottom-up design.

Top-down low-power design
For a hierarchical low-power design, one of the first decisions that we must make is whether to code the power intent file in a top-down or bottom-up fashion. In a top-down flow, the designer codes the full-chip power intent and verifies it through low-power structural and functional checks. After successful verification, the designer can partition the full-chip power intent and write it out for each sub-block. The block designers take these block-level power intent files and implement the sub-blocks. In a bottom-up flow, the block-level power intent is coded first. After that, the full-chip power intent is formed by merging all the block-level power intent files.

We discussed earlier how the power domains, states, and power modes tend to follow from the high-level system functions and architecture. This implies that top-down is the way to go, but there are other reasons that often make top-down the best choice. First, coding the full-chip power intent is much easier than coding the block-level power intent. The reason is that we can use abstraction and successive refinement to our advantage.

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