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Achieving early and accurate power analysis

Posted: 18 Apr 2012     Print Version  Bookmark and Share

Keywords:Common Power Format  Register Transfer Language  power analysis 

Power is receiving an increasing share of attention. Innovation, fuelled by the information and internet age, poses new challenges for electronic systems across a spectrum of applications. Mobile devices continue to break new frontiers of functional integration. Phones are now your email, social networking interface, video and music player, gaming device, camera, GPS, and more – all rolled into one. Yet the smart phone must survive through the day, and hopefully longer, without having to recharge the battery. Data centres and cloud computing grapple with power and carbon footprints as they move and process incredible amounts of data back and forth, consuming electricity to the order of 1-2% of the total that the entire world consumes. Advances in fabrication technology have made it possible for processors and system-on-chips (SoCs) to boast of over three-billion transistors, also pushing the limits of power density, integrity and reliability.

To address these challenges, power related design decisions are now being made throughout the product development cycle. Yet it is the early decisions that primarily govern the power and energy profile of a product. It is not surprising that key choices include how the design is partitioned into hardware versus software, the design architecture, and even to determine how the software controls the hardware. Once the design architecture is locked in, the most power-efficient implementation may lose out to an alternative more power-efficient architecture, even if the alternative is implemented half as well.

If the impact on power reduces when you go down levels of design abstraction, then predicting power with accuracy is the challenge at the higher levels of abstraction. It is unreasonable to expect the power numbers from a mostly untimed transaction-level design model to closely match numbers from a post-implementation design representation. At the same time, early power numbers must offer sufficient accuracy to evaluate design trade-offs relevant to the design abstraction level.

Models to the rescue
The semiconductor industry has long benefited from models that enable reasonable design cycles for the largest and most complex of designs. Functional, electrical, physical, and additional views are created for the building blocks relevant to different levels of design description. The models include enough information enabling decisions at each level while removing details that don't apply, providing capacity while maintaining the required accuracy. Models have continued to evolve; keeping up with the demands from technology advancements such as shrinking geometries and breakthrough techniques including three-dimensional integrated circuits (3D-ICs).

Power is a significant design consideration with multiple facets encompassing power budgets, power distribution network and integrity, thermal, and reliability. Recently, there have been well publicized standardisation efforts involving the specification and verification of a design's low-power intent through the Common Power Format (CPF) and Unified Power Format (UPF). However, standard models for analysing power consumption are targeted at when post-synthesis gate-level netlists are available. Typical models available today are not nearly sufficient enough to offer reliable accuracy for early analysis. In order to be sufficiently accurate, early analyses must account and model the power-significant aspects of downstream design transformations and details. Let's examine the challenges for digital hardware power analysis at the Register Transfer Language (RTL) design stage. But first, why RTL?

Early RTL power analysis
Traditionally, power is analysed when a design netlist mapped to a particular technology is available. On one hand, modern flows no longer "design" by manipulating gates. On the other hand, early transaction-level power analysis can enable significant architectural power exploration benefits, but that methodology is still evolving for most mainstream users. RTL delivers the best trade-offs between accuracy and the ability to design for low-power. Here are some of the key advantages.

Performance and capacity: RTL power analysis can offer 10X or more productivity as compared to gate-level power analysis; power numbers are available within hours versus days or weeks, even for multi-million instance designs. Some of the performance benefit is a reflection of the fewer design elements that are required to be processed at RTL versus gates. More significantly though, it is from eliminating the overhead to generate the data necessary for gate-level power analysis. It can take over 10 days to go through the implementation flow for a typical microprocessor, versus measuring power at RTL within a couple of hours.

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