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3D IC test vehicle ensures performance, yield

Posted: 30 Mar 2012     Print Version  Bookmark and Share

Keywords:test vehicle  3D IC  manufacturing process 

Altera Corp. and Taiwan Semiconductor Manufacturing Co. Ltd (TSMC) team to use TSMC's Chip-on-Wafer-on-Substrate (CoWoS) integration process to develop what they claim is the world's first heterogeneous 3D IC test vehicle.

According to the companies, TSMC's integrated CoWoS process provides chip companies developing 3D ICs an end-to-end solution that includes the front-end manufacturing process as well as back-end assembly and test solutions.

Altera touts itself as the first semiconductor company to develop and complete characterisation of a heterogeneous test vehicle using TSMC's CoWoS process. This and additional test vehicles enable Altera to quickly test the capabilities and reliability of 3D ICs to ensure they meet yield and performance targets, stated the company.

With regard to heterogeneous 3D ICs, Altera plans to develop device derivatives that allow customers to mix and match silicon IP based on their application requirements. The company also intends to integrate various technologies with an FPGA, including CPUs, ASICs, ASSPs, memory and optics. Altera's 3D ICs claim to enable customers to differentiate their applications by leveraging the flexibility of the FPGA, while maximising system performance, minimising system power and reducing form factor and system cost.

CoWoS is an integrated process technology that attaches device silicon chips to a wafer through a chip on wafer (CoW) bonding process. The CoW chip is attached to the substrate (CoW-On-Substrate) to form the final component. By attaching the device silicon to the original thick wafer silicon before it finishes the fabrication process, manufacturing-induced warping is avoided. TSMC plans to offer CoWoS as a turnkey manufacturing service.





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