Global Sources
EE Times-India
Stay in touch with EE Times India
 
EE Times-India > Power/Alternative Energy
 
 
Power/Alternative Energy  

AUTOSAR timing models reduce ECU risks

Posted: 16 Mar 2012     Print Version  Bookmark and Share

Keywords:AUTOSAR  electronic control unit  Timing analyses 

The estimate of the expected load is a first indication for the feasibility of a system, but it is not sufficient. Integration and scheduling effects like jitter, data path/timing chain latencies, temporary load peaks etc. are not being considered in a mere load analysis and have to be analysed separately.

Task generation, scheduling analysis
Based on the set of functions (runnables in AUTOSAR terminology), we are able to build a first virtual task schedule. Hereby we follow a scheduling concept suitable for the project, for example:

 • Runnables with the same cycle time are grouped in one task
 • The shorter the cycle time, the higher the task priority
 • The task deadline matches the cycle time (no multiple activations)

In AUTOSAR, this information is maintained in the RTE and OS configuration. Virtual task generation is therefore easily automated and can be extended with project specific rules.

The virtual task schedule allows to perform a scheduling analysis in order to determine the tasks? response times (the time span between a task's activation and its completion). Preemptions by tasks with higher priority are considered, which is an essential integration effect. Typically, each task has to be executed completely before its next activation (implicit deadline). If this is not the case, task activations may get lost during runtime, and functional correctness may be violated. In early development phases, the response times should be about 30 – 50% below deadline to keep sufficient space for extensions.

If a deadline is missed, respective measures have to be taken, for example increasing the cycle time of a runnable if this is possible. Code optimisation may allow reducing runnable execution times which not only reduces their own response time but also the response times of interrupted tasks. Additionally, selecting a faster CPU will speed up the complete system. An automation of this scheduling analysis enables fast exploration of different optimisation options. The scheduling analysis tool SymTA/S offers this automation and reduces the risk of late and costly design modifications.

When the individual runnable response times are within the permitted limits, the next step is the analysis of the data paths?/timing chains? latencies.

Figure 3: Load : SymTA/S Timing model with load, schedule, and data path/timing chain analysis.

Data path/timing chain analysis
Data paths/timing chains describe the communication between runnables and are comparable to signal paths/signal flows in Simulink or ASCET. The communication between runnables is realised via memory-based communication (data produced by a runnable is read by the next runnable in the chain). The example from figure 1 shows the three data paths/timing chains WK1, WK2, and WK3 which all start at a sensor S and end at an actuator A. In practice, such data paths/timing chains are subject to timing constraints like maximum reaction times or controller dead times. These data paths/timing chains can be easily specified in SymTA/S.

A data path's/timing chain's latency depends on the response times of the individual runnables, buffering periods between runnable executions, up and down sampling effects while changing cycle times etc. As the runnables? response times are influenced by preemptions by tasks with higher priority, the data path/timing chain latencies are likewise influenced by scheduling effects. The Gantt chart in the right lower corner of figure 3 shows this for data path/timing chain WK3.

Timing analysis with SymTA/S allows to determine a data path's/timing chain's latency considering all influencing factors. A comparison with the deadline shows if the latency is good enough or close to the limiting value or even above it. If the latter is the case, appropriate measures have to be taken to reduce the latency.

 First Page Previous Page 1 • 2 • 3 Next Page Last Page



Comment on "AUTOSAR timing models reduce ECU ris..."
Comments:  
*  You can enter [0] more charecters.
*Verify code:
 
 
Webinars

Seminars

Visit Asia Webinars to learn about the latest in technology and get practical design tips.

 

Go to top             Connect on Facebook      Follow us on Twitter      Follow us on Orkut

 
Back to Top