Global Sources
EE Times-India
Stay in touch with EE Times India
 
EE Times-India > Embedded
 
 
Embedded  

AUTOSAR timing models reduce ECU risks

Posted: 16 Mar 2012     Print Version  Bookmark and Share

Keywords:AUTOSAR  electronic control unit  Timing analyses 

AUTOSAR has been introduced as an automotive standard for electronic control unit (ECU) software development. It is now used in series projects either in version 3.2 or 4.0 (including Timing Extensions), depending on the OEM. From the software development perspective, AUTOSAR is already increasing productivity tremendously through standardisation.

However, from the system development perspective, key questions remain:

 • Feasibility: How much software can be handled by the ECU? Will all real-time requirements /timing constraints be fulfilled?
 • Safety/Availability/Expendability: How to avoid late and costly design modifications?
 • Documentation of real-time capability and requirements (including requirements specifications)

The goal is to have a system integration available at the end of the development which fulfils the above mentioned requirements, which uses the ECU resources in the best way, and which can accommodate extensions. The steps to this system integration include the mapping of functional architectures to software architectures, the creation of the Run-Time Environment (RTE) and OS configuration (schedule), and the integration of basic software (BSW) elements.

When it comes to securing real-time capability, the creation and verification of the ECU configuration (including runnables mapping, task layout, and schedule configuration) is particularly important. Timing analyses help to evaluate and document configurations, and to specify timing requirements for suppliers as necessary. Furthermore, they provide the basis for pending design decisions.

Suitable timing analysis approaches already exist and are widely in use. The most important aspects here are the CPU load (the load broken down into software components, tasks, and runnables) and the relationship between data paths/timing chains and the software architecture. Timing requirements for timing chains and the scheduling of all the functions to be integrated are equally important.

Load, cycle times and execution times
The overall load of a CPU is the sum of the load of all executed functions and components. The load of a single function is the quotient of the function's execution time and cycle time.

Figure 1: Software architecture with timing information and data paths/timing chains.

A function's cycle time is known from function modelling, for example in Matlab/Simulink or ASCET. It is described as cycle or sample time. In case of non-periodic processes, the activation frequencies can be derived by simulating the functional model.

To determine the execution time of a function, several approaches are available, depending on the development phase. Execution time estimations from previous projects may be used at the beginning of the development. Budgeting is another commonly used approach. Once first implementations are available in the course of the project, they can be measured using processor simulators (for example by VAST), prototype hardware or later on the real target hardware (using for example Gliwa?s T1). Static execution time analysis (for example by AbsInt) provides absolutely reliable upper execution time bounds.

Figure 2: Load analysis.

Figure 1 shows an example with three software components (SWCs) with respectively several runnables and the respective execution times (et) and cycle times (ts: time sample). Figure 2 shows the result of a load analysis for the complete system (71%) as well as for the single contributing parts.

Through a more and more detailed description of the system, the execution time of single functions and components becomes more precise during the course of the project. The load model is refined during the course of the project as well. Hence critical load situations can be identified at an early stage and specific countermeasures, for example through reducing execution times and/or increasing cycle times can be implemented.

1 • 2 • 3 Next Page Last Page



Comment on "AUTOSAR timing models reduce ECU ris..."
Comments:  
*  You can enter [0] more charecters.
*Verify code:
 
 
Webinars

Seminars

Visit Asia Webinars to learn about the latest in technology and get practical design tips.

 

Go to top             Connect on Facebook      Follow us on Twitter      Follow us on Orkut

 
Back to Top