Stay in touch with EE Times India

EE Times-India > Power/Alternative Energy

Power/Alternative Energy

Power tip: Managing high dI/dt load transients (Part 1)

Posted: 27 Feb 2012     Print Version

Keywords:central processing units  power supply  voltage source

With many central processing units (CPUs), specifications indicate that the power supply must be able to provide large, rapidly changing output currents, typically as the processor changes operating modes.

For instance, in a 1V system, the requirement may be to stabilise the supply voltage within three per cent for a 100 A/µsec load transient. The key to attacking this problem is to realise that this is not just a power supply problem but a power distribution system problem as well, and the two become intertwined in the solution.

The implication of these high di/dt requirements is that the voltage source must have very low inductance. Rearranging the following expression and solving for the allowable source inductance:

There can be only 0.3 nH of inductance in the path of the rapid load-current transient. For comparison, the inductance of a 0.25 cm-wide (0.1 inch) circuit-board trace on a four-layer board has an inductance of about 0.7 nH/inch (0.3 nH/cm). The typical inductance of a wire bond within an IC package is in the 1 nH range, and vias in a printed circuit board are in the 0.2 nH range.

There also is a series inductance associated with bypass capacitors as illustrated in the figure. The top curve is the impedance of a single 22µF, X5R, 16V, 1210 ceramic capacitor mounted on a four-layer circuit board.

 Figure: Parasitics in parallel capacitors impedance diminish effectiveness.

As expected, below 100kHz, the impedance drops with increasing frequency. However, there is a series resonance at 800kHz where the capacitor begins to turn inductive. The inductance, which can be calculated from the value of the capacitor and the resonant frequency, is equal to 1.7 nH which is well above our goal of 0.3 nH. Luckily, you can parallel capacitors to reduce the effective ESL.

The bottom curve in the figure is the impedance of two parallel capacitors showing a reduction in impedance. One interesting thing is that the resonance has shifted slightly lower, which indicates that the effective inductance is not exactly one half. Based on the resonant frequency, the new inductance is 1.0 nH or a 40 per cent reduction in the ESL for two inductors in paralle, rather than an expected 50-per cent drop. This effect can be attributed to two causes: an interconnect inductance, and a mutual inductance between the two capacitors.

1 • 2

Comment on "Power tip: Managing high dI/dt load ..."
Comments: *  You can enter [0] more charecters.

Top Ranked Articles

Webinars

Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Search EE Times India
Services

﻿