Avago, TI showcase 100GE solutions
Avago is announcing a 25Gbps serdes that can support transmissions across more than a metre of a backplane and up to five metres of copper cables. It will also demonstrate a 32Gbps chip, likely aimed at next-generation Fibre Channel storage networks.
TI is rolling out a line of ten 12.5Gbps signal conditioners that drive signals across copper cables over distances of up to seven meters. The components aim to replace larger, more expensive and power hungry PHY chips.
Both companies are using the latest process technologies and signal integrity techniques to hit new milestones. They join an industry focused on responding to the need to carry ever more data over networks while keeping a lid on power and cost.
Many of the chip, board and cable companies at DesignCon aim to enable 100G Ethernet products that uses four lanes running at 25Gbps. The products set to ship late this year will provide reductions in cost, size and power compared to today's 100GE systems that use ten 10Gbps lanes.
Sanjay Gajendra, senior product manager, TI, said, "The adoption of 100GE is happening much quicker than we anticipated with the rise of things like LTE networks and iPads." He explained further, "We still believe mass production of the next-gen Ethernet products will be at the end of the year, but a few vendors will demo prototypes earlier."
Frank Ostojic, general manager, ASIC group, Avago, commented, "The bandwidth needs of OEMs are going up incredibly every year." He added, "25G will require a system level approach and coordinated work in a close partnership among the board, chip and package suppliers—it will be a kind of chipset approach."
Multiple networking and telecom companies are already designing ASICs that will tape out over the next several months with Avago's long-reach 25G serdes. The chips comply with the latest 25G standards from the Optical Internetworking Forum and hit new lows in latency and power consumption, numbers that Avago is keeping under wraps.
"You need 28nm process technology to make this work," Ostojic said.
Avago's 25G serdes, which will eventually appear in the company's standard products, employ proprietary techniques in clocking and decision equalisation feedback (DFE). Avago also is expected to demo a 100G kit that can be used to optimise designs with any vendor's serdes including competitors such as Finisar, IBM, LSI and STMicroelectronics.
TI's signal conditioning group, formerly part of National Semiconductor, is using DesignCon to launch a line of 12.5G repeaters and retimers, saving news of its planned 25G parts for later in the year.
The repeater chips consume as little as 65mW driving a 10G channel; the retimers consume about 150mW. They are meant to serve board, copper or optical cable applications across a range of protocols including Ethernet, Fibre Channel and Infiniband.
TI uses a proprietary BiCMOS SiGe process to hit the low power figures. Algorithms on the chips measure signals and apply equalisation as needed on the fly.
The company hopes its the signal conditioners will replace external physical-layer chips given ASICs are increasingly building in the serdes and protocol processing functions once handled by the PHYs. OEMs can save up to 90 per cent of the power and 75 per cent of the board space used by the external PHYs by taking such an approach, said TI's Gajendra.
Other PHY makers such as Broadcom and Marvell are likely to offer their own twists on integrated chips and different value propositions. Gajendra said they are still likely to drive greater power consumption.
TI must also compete with other repeater and retimer vendors such as Gennum. Both companies gave demos last year at DesignCon of 25G products in the works.
Engineers are aiming for 25G products supporting 30dB loss, said Gajendra. Products demonstrated to date hit about 25dB, he said.
- Rick Merritt
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