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How to employ critical area analysis

Posted: 20 Jan 2012     Print Version  Bookmark and Share

Keywords:design-for-manufacturing  Critical area analysis  Memory redundancy 

As shown in figure 2, critical area increases with increasing defect (particle) size. At the limit, the entire area of the chip will be critical for a large enough defect size. In practice, most fabs limit the range of defect sizes that can be simulated, based on the range of defect sizes they can detect and measure with test chips or metrology equipment.

Defect densities
Semiconductor fabs have various methods for collecting defect density data. In order to be used for CAA, the defect density data must be converted into a form compatible with the analysis tool. The most common format is the simple power equation shown in (1). In this equation, k is a constant derived from the density data, x is the defect size, and the exponent q is called the fall power. The fabs curve-fit the opens and shorts defect data for each layer to an equation of this form to support CAA. In principle, a defect density needs to be available for every layer and defect type to which CAA will be applied. However in practice, layers that have the same process steps, layer thickness and design rules typically use the same defect density values.

Defect density data may also be provided in table form where each specific defect size listed has a density value. A simplifying assumption is that outside the range of defect sizes the fab has data for, the defect density is 0.

Figure 2: Critical Area CA(x) in square microns as a function of defect size in nanometers for one defect type.

Calculation of ANF
To determine ANF for a design, a tool that supports CAA, such as Calibre, is used to extract the Critical Area CA(x) for each layer over the range of defect sizes. This is done by measuring the actual layout and determining all the areas where a particle of a given size could result in a failure. The CA(x) and the defect density data D(x) are then used to calculate the expected average number of faults (ANF) according to (2). This calculation is performed by the tool using numerical integration. The dmin and dmax limits are the minimum and maximum defect sizes according to the defect data available for that layer.

In most cases, the individual ANF values may simply be added to arrive at a total ANF for all layers and defect types. Note that ANF is not strictly a probability of failure, as ANF is not constrained to be less than or equal to 1.

Calculation of yield
Once the ANF has been calculated, it is usually desirable to apply one or more yield models to make a prediction of the Defect Limited Yield (DLY) of a design. Naturally, DLY cannot account for parametric yield issues, so care must be taken when attempting to correlate to actual die yields. One of the simplest, most widely used yield models is the Poisson model (3).

ANF and yield for cut layers
Calculation of ANF and yield for cut layers (contacts and vias) is generally simpler than for other layers. In fact the classic CAA technique described above need not be used at all. Most foundries define a probabilistic failure rate for all single vias in the design, and assume that via arrays do not fail. This simplifying assumption neglects the problem that a large enough particle will cause multiple failures, but it greatly simplifies the calculation of ANF as well as reducing the amount of data needed from the fab. All that is needed is a sum of all the single cuts on a given layer, and the ANF is simply calculated as the product of the count and the failure rate (4).


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