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Managing single event effects in FPGAs, ASICs and processors (Part 2)

Posted: 09 Jan 2012     Print Version  Bookmark and Share

Keywords:single-event effects  ASICs  FPGAs 

Using the essential bits output with SEM IP, which detects and corrects upsets, allows the system to ignore non-essential bit upsets. Non-essential bits are still corrected to prevent accumulation of errors, but the design can continue to operate without further intervention. If an essential bit is upset, then that bit is corrected and the user design can determine whether or not a device reset is prudent, depending on architectural knowledge of the design and the effects of persistent and non-persistent errors. Using this technology, the effective FIT rate of a full device is reduced to 33% or less.

Even if an essential and critical bit upset is corrected, an error can still propagate. DMR/TMR and other architectural techniques are required to guarantee uninterrupted operation. An upset that affects a feedback or decision path could propagate or place the design in an unintended mode prior to correction of the upset configuration bit. For this reason, short of robust architectural mitigations, it is prudent to correct all upset bits, and then, if it is an essential bit upset, internally reset the device. Xilinx is continuing to develop technologies that can enhance the fidelity of SEU responses.

Recommendations
Xilinx enables users to employ various levels of SEU protection and recommends that designers:

1. Assess the soft error data for device families.8

2. Select a device family that supports SEM IP (Virtex-5 FPGAs and later).8

3. Employ the SEU FIT Rate Calculator (available from Xilinx) to assess the soft error FIT rate and MTBF for the design and target device with the level of device utilisation and environmental conditions that are expected. This is a preliminary assessment tool.

4. Complete the normal design process incorporating the SEM IP.

5. Simulate the design and use the SEU fault-injection simulation capability to verify the design. They should also simulate forced invalid states in state machines.

6. Use the ISE? Design Suite 13.2 (or later) essential bits output data to assess the estimated SEU rate for the design. These are refinements that can be fed back into the FIT Rate Calculator to yield a more accurate estimate of the design FIT rate. The Essential Bits outputs can be used with certain versions of the SEM IP and target devices to reduce unnecessary handling of false-positive SEU hits. 8

Systems that utilise sub-90 nm geometries, products like ASICs and FPGAs, in any avionics or high-reliability application must adopt proper techniques to mitigate the susceptibility of such technologies to SEEs. FIT rate estimates can be used to assess the MTBF of these technologies for the proper mitigation at the device and system level. Any mitigation strategy ultimately needs to address trade-offs that include area, performance, detection time, and correction time. These factors need to be balanced against fixed and variable costs as well as system safety and reliability costs.

References
1. ReStore: Symptom-Based Soft Error Detection in Microprocessors, Nicholas J. Wang, Sanjay J. Patel, University of Illinois
2. Clock, Flip-Flop, and Combinatorial Logic Contributions to the SEU Cross Section in 90 nm ASIC Technology, David L. Hansen, Eric J. Miller, Aj Kleinosowski, Kirk Kohnen, Anthony Le, Dick Wong, Karina Amador, 2009, IEEE Transactions on Nuclear Science
3. Azambuja, Lapolli, et al., "Detecting SEEs in Microprocessors Through a Non-Intrusive Hybrid Technique," IEEE Transactions on Nuclear Science (2011).
4. Nathaniel H. Rollins and Michael J. Wirthlin, "Software Fault-Tolerant Techniques for Softcore Processors in Commercial SRAM-Based FPGAs," NSF Centre for High-Performance Reconfigurable Computing (CHREC), Brigham Young University (2011).
5. Johnson, Morgan, et al., "Detection of Configuration Memory Upsets Causing Persistent Errors in SRAM-based FPGAs," 7th Annual Military and Aerospace Programmable Logic Devices International Conference (2004).
6. Mukherjee, Weaver, et al., "A Systematic Methodology to Compute the Architectural Vulnerability Factors for a High-Performance Microprocessor," Proceedings of the 36th International Symposium on Microarchitecture (2003).
7. Duan, Li, et al., "Versatile Prediction and Fast Estimation of Architectural Vulnerability Factor from Processor Performance Metrics," Proceedings of the 15th IEEE International Symposium on High-Performance Computer Architecture (HPCA-15), Raleigh, NC (2009).
8. Xilinx Avionics website

About the author
Dagan White has over 15 years of multi-disciplinary engineering experience within the A&D industry. His electronics and systems development work has spanned mixed-signal electronics hardware design and FPGA development for lidar systems and radiometers. He has worked for Lockheed Martin Coherent Technologies and ITT Geospatial Systems, and is now with Xilinx as staff systems architect for avionics, tasked with leading FPGA avionics solutions development; current areas of focus include DO-254, SEU, IP, and design flows. Dagan holds a BSEE and an MBA from the University of Colorado.

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