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Creating HD FPGA-based graphics controller

Posted: 18 Oct 2011     Print Version  Bookmark and Share

Keywords:graphics controller  FPGA  clock 

One of our clients recently asked us for a solution to display graphics on LCD monitors. We were informed that any data was to be is generated by a separate device and fed to the graphics controller using an external microcontroller. Our client already had the rest of the system made and working, so switching to some Android/PC based system wasn't an option. Also, the ability to add custom-made features was a big pro for an FPGA-based solution.

At first this sounded like a job for our LAVA 10 SVGA controller, but then some additional requirements started to appear:
� The device needs to be able to display graphics in different resolutions starting from 1024x768 to 1920x1080
� It needs to have separate layers that can be switched on and off and can be merged together to create more complex picture.
� The layers need to have some transparency features
� A hardware cursor would be nice

 HD graphics controller

Figure: Here's a block diagram of the HD graphics controller.

OK, first of all some math needs to be done. The most demanding use-case involved the highest resolution. To display one frame we need 1920 * 1080 * (number of bytes/pixel). At this point we agreed that 256 colours that could be selected from an 18bit palette (offering 262,144 colours in all) would be sufficient. This results in over 2 MB per frame, which means that a refresh rate of 60Hz will require 120 MB/s just for rendering the current frame (without any additional operations).

When adding the additional bandwidth required to perform operations on separate layers (each of which also has a 1920 x 1080 resolution), we decided to look for a memory and memory controller that can work with and average bandwidth of more than 200 MB/s.

This left us with a choice: (a) Trying to go with SDR memory, which would require us to optimise the memory controller trying to cut the latencies and use bursts as much as possible, or (b) switch to DDR memory, thereby providing some margin in the bandwidth for more complex operations and also saving some logic in the FPGA.

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