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Address power issues in embedded apps using dual OS

Posted: 11 Jul 2011     Print Version  Bookmark and Share

Keywords:DSP  operating systems  Adaptive voltage scaling 

Energy consumption is becoming more of a concern as it is gaining a growing larger percentage of the overall operating costs. Imagine superstores with lines and lines of check-out lanes, each with a cash register, a credit-card reader, a scanner and a weight measuring station.

It is a waste if these equipments are not designed to be energy efficient with abilities to power down between customers or during non-operating hours. When multiplied by the number of stores, the number of cities and the operating life of the product, the total accumulated portion of the energy bill that could be saved is in the crores.

Many of today's operating systems, like Linux, come with power management support. The features have been available on the mainstream kernel since Linux made headways to lower power portable devices like smart phones, tablets and ebook readers. So even though your design is a plugged-in appliance, you can embrace the "go green" initiative from the ground up by taking advantage of the power management features that are already in place and incorporate them.

In this article I will first review power savings techniques available with today's powered (i.e. plugged-in) system-on-chip (SoC)-based embedded systems and quickly move on to the discussion of how two operating systems (OSes), each with its own power methodologies, can cooperate at the system level to provide power management services.

Chip and system hardware issues
There are two different components to the power equation from a silicon process stand-point: static, sometimes referred to as standby), and active. Static power is affected by leakage mainly and increases with temperature and supply voltage. Since leakage is a natural phenomenon that comes with shrinking process technology, the only way to really eliminate it is to shut that component down. Within the SoC, tactics employed so far include power islands, enabling part of the SoC to completely shut down.

On the other hand, active power, which does increase with supply voltage, but not temperature, depends on chip activity. Strategies here include:

1—Dynamic voltage and frequency scaling (DVFS), where the voltage and frequency can be dynamically adjusted to adapt to the performance required
2—Clock domain to gate off unused peripheral
3—Dynamic power switching (DPS), where software can switch between power modes based on system activity. The "software" is usually part of the operating system
4—Adaptive voltage scaling (AVS), a closed-loop, hardware and software cooperative strategy to maintain performance while using the minimum voltage needed based on the silicon process and temperature

From the system standpoint, operations needed for power management include the ability to:

1—Go to standby (user-application- or system-initiated system service)
2—Hibernate to memory or storage (user-application- or system-initiated system service)
3—Suspend and resume (user-application-initiated system service)
4—Transition to different power profiles (user application condition or state, system initiated and controlled)

Power can also be affected how the application code is designed. For example, input/output (I/O) buffers at the pin, memory controllers and especially double data rate (DDR) need to drive current. Unnecessarily moving data in and out of the SoC can waste energy.

Let's take a look at the block diagram of a typical modern embedded system as shown in figure 1. The processor is highly integrated and includes several types of processors and accelerators for application-specific needs as well as all the I/O peripherals to get the data in and out.

The system board has external voltage regulators for the different power rails in addition to battery and clock management support integrated circuits (ICs). It also contains external I/O modules and hot swappable devices.

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