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Flex FEC ASIP sol'n targets software-defined radios

Posted: 14 Jun 2011     Print Version  Bookmark and Share

Keywords:c-programmable  fec  forward error correction 

Imec and Target Compiler Technologies release a C-programmable flexible FEC (forward error correction) solution for software-defined radios that competes in area and throughput with dedicated fixed-function hardwired implementations, yet offers the flexibility to support multiple standards thanks to software programmability.

The C-programmable flex FEC ASIP (application-specific instruction-set processor) template supports LDPC (low-density parity check), Turbo and Viterbi decoding. Imec designed and optimised the ASIP architecture and generated a matching software development kit, using IP Designer, Target's tool-suite for ASIP design.

Imec's ASIP architecture template can be instantiated for different standards to perform channel decoding. Various algorithmic-architectural co-optimisations enabled parallelisation of the algorithms to meet the high throughput and latency requirements in a flexible processor. The solution meets throughput and latency specifications ranging from connectivity (WLAN 802.11n, 802.11ac) to broadcasting (DVB-T2/S2, CMMB, DVB-SH) and cellular standards (3GPP-LTE, 802.16e).

Target Compiler Technologies' IP Designer tool-suite enabled the design-time architectural exploration and optimisation of Imec's flex FEC solution and allowed a quick validation of the impact of architectural changes on throughput, latency, silicon area and power consumption. IP Designer automatically generated an optimising C-compiler to compile the multi-standard FEC algorithms on the specialised FEC architecture exploiting the available instruction-level parallelism, and an instruction-set simulator to validate and profile the code running on the architecture.

The flex FEC template was instantiated for WLAN, WiMAX, 3GPP-LTE and DVB-S2/T2. A low-power register-transfer level hardware implementation of the core was automatically generated with the IP Designer tools, which resulted in a total core area and throughput competitive with state-of-the-art dedicated fixed-function hardwired solutions. The generic template, supporting both turbo and LDPC decoding can be pruned aggressively in case of LDPC decoding only, leading to substantial additional savings in area and power consumption.





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