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Industry catches on to 3D chip mania

Posted: 08 Apr 2011     Print Version  Bookmark and Share

Keywords:through-silicon-via  TSV-based 3D chips  3d chip project  3D interconnection of wafers 

Today, mobile DRAM is based on a technology called low-power double data rate 2 (LPDDR2). Beyond LPDDR2, Samsung and others are pushing wide I/O DRAM for mobile applications. Wide I/O will evolve in two phases. The first wide I/O DRAMs are four-partitioned devices, which will be stitched together via micobumps. They are expected to appear in 2013.

In the future, vendors hope to stack multiple wide I/O DRAMs using TSVs. Some say those devices will appear in 2014 or 2015. Some believe the technology will appear later than sooner. Due to the complexity and costs, TSV-based wide I/O DRAM will not arrive until "the second half of the decade," said Sharon Holt, senior vice president and general manager of the Semiconductor Business Group at Rambus Inc.

Holt also does not believe the industry will directly migrate from LPDDR2 mobile DRAM to wide I/O DRAM. LPDDR2 mobile DRAMs began shipping last year, but wide I/O DRAM will not appear for some time.

As a result, there is a time gap between the two technologies. Not surprisingly, Rambus is pushing mobile XDR, one of the many next-generation mobile DRAM technologies in the market.

3D mania hits market
During a keynote address at the GSA event, Holt also said that there could one day be a convergence between today's mobile and PC memory. In other words, some of the low-power technologies in mobile DRAM could migrate to PC DRAM, creating what Holt called a "unified memory system."

Others have a different idea. At the GSA event, Jim Elliott, vice president of marketing and product planning at Samsung Semiconductor Inc., said there could be a convergence in DRAM technology, but he noted that convergence involves a wide I/O product based on TSV.

But one of the problems with TSV is the lack of standards. In December, SEMI moved to reverse the problem by forming the Three-Dimensional Stacked Integrated Circuits (3DS-IC) Standards Committee.

To gather industry input and identify potential standardisation topics, SEMI is working with Sematech to identify areas of concern for 3D TSV integration. Sematech represents several companies, including Globalfoundries, HP, IBM, Intel, Samsung and United Microelectronics Corp. Other companies supporting the formation of the 3DS-IC Standards Committee include Amkor, ASE, IMEC, ITRI, Olympus, Qualcomm, Semilab, Tokyo Electron and Xilinx.

The 3DS-IC Standards Committee will initially consist of three Task Forces:

� Bonded Wafer Pair (BWP) Task Force: This group will create a standard for BWP, using SEMI M1 (Specifications for Polished Single Crystal Silicon Wafers) as a starting point. Sematech is the task force leader.

� Inspection and Metrology Task Force: With no existing standards in place, the group will seek to identify and create new standards that address deficiencies for metrology and inspection created by 3DS-IC. Semilab is the task force leader.

� Thin Wafer Carrier Task Force: Currently no standards exist so this group will identify and create new standards for thinned wafer carriers to address deficiencies created by 3DS-IC. Qualcomm is the task force leader.

Another task force is being formed, which will focus on a "single wafer used in a stack process," said James Amano, director of international standards at San Jose-based SEMI. That task force will be possibly led by Applied Materials Inc., he said.

The 3DS-IC Standards Committee met last week to hammer out the first standards for "wafer parameters" and other technologies, he said. A draft specification is due early next year, he said.


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