Industry catches on to 3D chip mania
Problems plaguing the through-silicon-via (TSV) technology have led many to question the feasibility and future of mainstream TSV-based 3D chips. Observers lament the technology's slow progress, claiming TSV seems stuck in the "power point" stage.
At the 2011 GSA Memory Conference in San Jose, California, four industry organisations—IMEC, ITRI, Sematech and SEMI—separately made presentations about the latest progress within their respective entities for 3D chips based on TSV.
A 3D working group within SEMI met for the first time last week to sketch out the initial wafer and tool standards for TSV technology. SEMI has three task groups within its 3D group. A fourth group is being formed, which may be led by Applied Materials Inc.
In a separate programme within Sematech, the chipmaking consortium is expanding its own 3D programme. One surprising chipmaker, Analog Devices Inc., is joining Sematech's 3D Design Enablement Centre. Altera, LSI, On Semiconductor and Qualcomm are also part of the centre.
A plethora of others are also scrambling to develop TSV-based technology, and for good reason: There are fears that IC scaling is becoming too costly for most chipmakers—or will end in the distant future.
So instead of scaling, there is another concept on the table: stack and connect devices in a 3D configuration using TSVs. For years, chipmakers have been talking about 3D chips based on TSVs. But except for select products—such as CMOS image sensors—the technology has not moved into the mainstream, due to costs, lack of standards and other factors.
In theory, 3D chips could evolve in two steps. The first step is a 2.5D scheme using silicon interposers. Then, eventually, the industry could move to TSV—if it can solve the multitude of problems with the technology.
Right now, there are several new and mainstream 3D chip projects in the works. For example, Semtech Corp. is working with IBM Corp. and its 3D TSV technology to develop a combination ADC and DSP platform. These two different technologies are connected through a single wiring layer on an interposer, which supports a bandwidth of greater than 1.3Tbps.
Last year, Xilinx Inc. announced the industry's first stacked silicon interconnect technology for delivering breakthrough capacity, bandwidth and power savings using multiple FPGA die in a single package for applications that require high-transistor and logic density. By embracing 3D packaging technologies and TSV for its 28nm 7 series FPGAs, Xilinx can address systems with resource requirements that are more than double the reach of the largest single-die FPGAs. Initial devices will be available in the second half of 2011.
In a separate effort, Hynix, Samsung and others have identified a new device vehicle that could propel TSV-based 3D chips into the mainstream: a wide I/O DRAM for cell phones, tablets and related products.
Wide I/O, a memory interface standard in review at JEDEC, defines a 512bit wide interface to increase the bandwidth between memory and logic. The interface operates at a peak data transfer rate of 12.8GBps, which is up to four times the performance of conventional low-power memory solutions.
|Related Articles||Editor's Choice|