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40nm SerDes IP supports multiple protocols

Posted: 10 Feb 2011     Print Version  Bookmark and Share

Keywords:integrated clocking  interface IC  40nm  Serialiser/Deserialiser 

Analog Bits launches a low power 40nm, high-speed Serialiser/Deserialiser (SerDes) IP that is programmable to support multiple protocols and small enough to be used in embedded SoCs.

The 40nm SerDes supports more than 100 lanes, from 1 to 12.5Gb per lane, on a single IC with a mere 5mw per gigabit per second per lane power consumption. Currently in production in multiple applications, it has been validated in over 30 industry standard protocols including PCI Express, SATA, XAUI, XFI, SGMII, and claims the lowest chip-to-chip communications latency.

SerDes technology converts between parallel and serial communications protocols and is of increasing importance in embedded SoC applications. According to a recent Semico Research report, it is projected that more and more IP sub-systems will appear featuring SerDes interfaces to move data quickly to other on-chip sub-systems and for high speed communications to the outside world.

Analog Bits' SerDes Interconnect is tested and currently available down to 40nm process geometries, with other nodes to follow.





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