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GUI-based compiler simplifies DDR PHY assembly

Posted: 31 Jan 2011     Print Version  Bookmark and Share

Keywords:PHY compiler  GUI-based tool  SoC design 

Synopsys Inc. releases a GUI-based DesignWare DDR PHY compiler for SoCs offering ease in assembly of a customised, high-performance DDR PHY.

The DesignWare DDR PHY compiler evaluates more than 60 variables and allows the evaluation of unlimited 'what-if' scenarios, supporting DDR2, DDR3, LPDDR and LPDDR2 SDRAMs. The output of the PHY compiler is a customised hard DDR PHY that is optimised for the target application.

Supporting the DesignWare DDR2/3-Lite, DDR 3/2 and DDR multi-PHY IP products, the DesignWare DDR PHY compiler's GUI steps the user through a series of decisions as they construct their DDR PHY from hard IP components, including application-specific DDR I/Os. Designers have control over multiple variables including supported DRAM types (such as DDR3, DDR2, Mobile DDR and/or LPDDR2), foundry and process node, memory channel width, power-to-signal ratios, core power requirements and other physical placement variables. The DesignWare DDR PHY compiler produces an instantly viewable image of the DDR PHY layout, a list of the pins, area, a power consumption report, placement scripts and an RTL model of the PHY.

Synopsys' comprehensive DesignWare DDR IP offering consists of digital controllers and PHY IP supporting DDR, DDR2, DDR3, Mobile DDR and LPDDR2. The DesignWare DDR PHY IP supports leading process technologies and includes a DFI 2.1-compliant interface. Synopsys' DesignWare Universal DDR Memory and Protocol Controller IP complement the DesignWare DDR PHY IP, offering a comprehensive DDR interface solution from a single IP vendor. Synopsys helps lower integration risk by providing high-quality DDR IP solutions that have been implemented in hundreds of applications and are shipping in volume production.

The DesignWare DDR PHY compiler is available to licensed customers of select DesignWare DDR PHY IP today.

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