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Trio of clock buffer families cut board space

Posted: 22 Nov 2010     Print Version  Bookmark and Share

Keywords:clock buffer  additive jitter  communication applications 

From Texas Instruments Inc. (TI) come three separate clock buffer families the CDCLVC11xx, CDCLVD12xx/21xx and CDCLVP12xx/21xx which are targeted at a variety of communication applications with frequency support of up to 2GHz (LVPECL), 800MHz (LVDS) and 250MHz (LVCMOS). The families boast of improved signal quality with lowest additive jitter and small-footprint QFN and TSSOP options.

These families of clock distribution buffers also save customers board space with small-footprint QFN and TSSOP options. In addition to supporting customers' general-purpose clock buffering and distribution needs, these devices also meet stringent additive jitter requirements for wireless infrastructure, data communications and telecommunications, medical imaging and industrial applications.

The CDCLVC11xx clock buffer family for LVCMOS output
This family offers low-skew, low-additive jitter which generate 2, 3, 4, 6, 8, 10 and 12 copies of LVCMOS clock outputs from a single LVCMOS input. Its low-additive jitter of less than 100fs RMS (12kHz—20MHz) boasts of improving clock signal quality by nearly 10x over the competition. Its low output skew of 50ps, maximum, provides up to five times better timing control among all outputs. The package modularity improves flexibility for various output configurations and simplifies board layout for multiple output requirements.

CDCLVD12xx/21xx clock buffer family for LVDS output
This family generates 4, 8, 12 or 16 copies of LVDS clock outputs from one of two selectable LVCMOS, LVDS or LVPECL inputs. The low-additive jitter of less than 300fs RMS (10kHz—20MHz) improves clock signal quality by nearly three times over the competition. It has a low output skew of 20ps, maximum (within same bank), which delivers up to 60 per cent better timing control among all outputs. Its universal input support eliminates the need for additional external discretes for signal level translation. The small package options in QFN-16/28/40/48 saves board space by up to 600 per cent compared to competitive devices.

CDCLVP12xx/21xx clock buffer family for LVPECL output
This family generates 4, 8, 12 or 16 copies of LVPECL clock outputs from one of two selectable LVCMOS, LVDS or LVPECL inputs. The low additive jitter of less than 100fs RMS (10kHz—20MHz) improves clock signal quality by 10 times over the competition.

It has low output skew of 15/20/25/30ps maximum for up to 40 per cent better timing control among all outputs. It also offers universal input support that eliminates the need for additional external discretes for signal level translation. Its small package options in QFN-16/28/40/48 saves board area by up to 600 per cent compared to competitive devices.

All the families, the CDCLVC11xx, CDCLVD12xx/21xx, and CDCLVP12xx/21xx are available now. Suggested resale price for the 4-output version in each family is Rs.40.20 ($0.90), Rs.127.31 ($2.85) and Rs.147.41 ($3.30), respectively, in quantities of 1,000.

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