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FPGAs offer flexible port configurations

Posted: 11 Nov 2010     Print Version  Bookmark and Share

Keywords:Virtex-6 HXT FPGAs  transceiver  optical communications 

Xilinx Inc. rolls out the Virtex-6 HXT FPGAs that support 40Gbit/s and 100Gbit/s line cards with flexible port configurations, including 1x40Gbit/s, 4x10Gbit/s, 1x100Gbit/s and 10x10Gbit/s. The company claims the performance of the Virtex-6 HXT device lets designers interface directly to optical modules without the need for external re-timers, thereby saving on BOM, power dissipation and board real estate.

The company says it has validated Virtex-6 HXT FPGAs interoperability with optical transceiver suppliers including Avago Technologies.

Xilinx Virtex-6 HXT devices seamlessly interface to industry standard SFP+, XFP, and CFP optical modules at line rates up to 11.18Gbit/s addressing next generation optical transport application needs. Plus, its jitter performance of <500fs rms random jitter at 11.18Gbit/s eliminates the need for external conditioning circuitry. The superior jitter performance provides the system designer the margin required to build robust high speed interfaces.

Devices features
Optimised for applications that require ultra high-speed serial connectivity, Virtex-6 HXT FPGAs offer the industry's highest serial bandwidth through a combination of 6.6Gbit/s GTX transceivers and 11.18Gbit/s GTH transceivers to enable next-generation packet and transport, switch fabric, video switching, and imaging equipment. To enable these applications, Virtex-6 HXT devices also feature a ground up design that is optimised for 10G signalling—including Transmit (Tx) pre-emphasis, Receive (Rx) linear equalisation and Decision Feedback Equaliser (DFE) to meet the tough jitter requirements. It offers lower jitter with superior DFE and EQ circuits, higher total transceiver count, more BRAM and highest number of Serdes capabilities. Its design topology isolates the high performance analogue circuits from the noisy digital logic and I/O providing superior noise performance. It is a ground up package design with all serial pins isolated from parallel I/O, in-package power planes and capacitors, and a sparse-chevron pinout resulting in 40dB of isolation between Tx and Rx and 30dB of isolation between channels. The Virtex-6 HXT FPGAs are now shipping and customers can start their designs immediately with the ISE Design Suite version 12.3.

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